Firestorm: SDIV (slow, 32-bit) measurements

Code:

  sdiv w0, w1, w2

Initialization

  mov w1, #0x7fffffff
  mov w2, #3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	2039	15	0	0	0	61	950	25	1000	1000	1000	53725	1	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	2	16	2	2	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	15	0	0	0	61	950	25	1000	1000	1000	53725	1	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	2	16	2	2	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	15	1	0	18	61	950	25	1000	1000	1000	53725	1	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	2	16	2	2	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	15	0	0	0	61	950	25	1000	1000	1000	53725	0	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	2	16	2	2	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	16	0	0	0	61	950	25	1000	1000	1000	53725	0	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	2	16	2	2	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	15	0	0	0	61	950	25	1000	1000	1000	53725	0	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	2	16	2	2	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	15	0	0	0	61	950	25	1000	1000	1000	53725	0	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	2	16	2	2	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	15	0	0	0	61	950	25	1000	1000	1000	53725	0	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	2	16	2	2	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	15	0	0	0	61	950	25	1000	1000	1000	53725	0	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	2	16	2	2	1980	1000	1000	2040	2040	2040	2040	2040
1004	2039	15	0	0	0	61	950	25	1000	1000	1000	53725	0	2039	2039	1801	3	1897	1000	1000	2000	2039	261	1	1	1001	1000	0	0	73	2	16	2	2	1980	1000	1000	2040	2040	2040	2040	2040

Test 2: Latency 1->2

Chain cycles: 2

Code:

  sdiv w0, w1, w2
  eor x1, x1, x0
  eor x1, x1, x0

Initialization

  mov w1, #0x7fffffff
  mov w2, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30204	100035	749	0	0	0	61	91261	25	30100	30100	30100	9493443	1	49	96955	0	100035	100035	95873	0	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	2003	3	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30205	100035	749	0	0	0	61	91261	25	30100	30100	30100	9493443	0	49	96955	0	100035	100035	95873	0	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	750	0	0	0	726	91261	25	30100	30100	30100	9493443	0	49	96955	0	100035	100035	95873	0	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	1	3	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	750	0	0	0	61	91261	25	30100	30100	30100	9493443	1	49	96955	0	100035	100035	95873	0	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	61	91261	25	30100	30100	30100	9493443	0	49	96955	0	100035	100035	95873	0	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	1910	0	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	61	91261	25	30100	30100	30100	9493443	0	49	96955	0	100035	100035	95873	0	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	1910	1	26	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	61	91261	25	30100	30100	30100	9493443	0	49	96955	0	100035	100035	95873	0	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	61	91261	25	30100	30100	30100	9493443	1	49	96955	0	100035	100035	95873	0	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	726	91261	25	30100	30100	30100	9493443	0	49	96955	0	100035	100035	95873	0	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	750	0	0	0	61	91261	25	30100	30100	30100	9493443	0	49	96955	0	100035	100035	95873	0	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30024	100035	749	0	0	0	61	91182	25	30010	30010	30010	9478767	0	49	96955	0	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	1890	0	6	16	5	6	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	2	0	0	61	91182	25	30010	30010	30010	9478767	0	49	96955	0	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	1890	0	5	16	5	6	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	0	0	61	91182	25	30010	30010	30010	9478767	0	49	96955	0	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	1890	0	5	16	5	3	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	0	0	61	91182	25	30010	30010	30010	9478767	0	49	96955	0	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	1963	0	5	16	5	4	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	750	0	0	0	61	91182	25	30010	30010	30010	9478767	0	49	96955	0	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	1890	0	4	16	4	5	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	0	0	103	91182	25	30010	30010	30010	9478767	0	49	96955	0	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	1890	0	4	16	4	5	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	0	0	61	91182	25	30010	30010	30010	9478767	0	49	96955	0	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	1890	0	5	16	3	5	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	0	0	0	726	91182	25	30010	30010	30010	9478767	0	49	96955	0	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	1890	0	3	16	5	3	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	750	0	0	0	61	91182	25	30010	30010	30010	9478767	0	49	96955	0	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	1	0	0	0	0	1890	0	5	16	5	5	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	750	0	0	0	61	91182	25	30010	30010	30010	9478767	0	49	96955	0	100035	100035	95885	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	0	0	1890	0	5	16	5	3	99714	30000	30010	100036	100036	100036	100036	100036

Test 3: Latency 1->3

Chain cycles: 2

Code:

  sdiv w0, w1, w2
  eor x2, x2, x0
  eor x2, x2, x0

Initialization

  mov w1, #0x7fffffff
  mov w2, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	18	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30204	100035	749	0	0	0	0	0	1581	91261	25	30100	30100	30100	9493443	1	49	96955	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	2	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	750	0	0	0	0	0	61	91261	25	30100	30100	30100	9493443	1	49	96955	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	0	0	61	91261	25	30100	30100	30100	9493443	1	49	96955	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1935	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	0	0	2727	91261	25	30100	30100	30100	9493443	1	49	96955	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	0	0	61	91261	25	30100	30100	30100	9493443	1	49	96955	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	0	0	61	91261	25	30100	30100	30100	9493443	1	49	96955	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	0	0	726	91261	25	30100	30100	30100	9493443	1	49	96955	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	0	0	61	91261	25	30100	30100	30100	9493443	1	49	96955	100035	100035	95873	3	96242	30205	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	749	0	0	0	0	0	513	91261	25	30100	30100	30100	9493443	1	49	96955	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	0	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036
30204	100035	750	0	0	0	0	0	61	91261	25	30100	30100	30100	9493443	1	49	96955	100035	100035	95873	3	96242	30100	30200	60200	100035	193	1	1	30201	100	99	100	30100	100	1	0	0	0	0	1910	1	17	1	1	99722	30000	30100	100036	100036	100036	100036	100036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 8.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
30024	100035	749	1	1	0	2	68	91182	25	30010	30010	30010	9478767	0	49	96955	100035	100035	95885	0	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	153	0	1894	17	16	14	17	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	1	1	0	2	68	91182	25	30010	30010	30010	9478767	0	49	96955	100035	100035	95885	0	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1894	16	16	18	20	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	1	1	0	2	327	91182	25	30010	30010	30010	9478767	0	49	96955	100035	100035	95885	0	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1894	17	16	16	20	99714	30000	30010	100036	100036	100036	100075	100036
30024	100035	749	1	1	0	2	73	91182	25	30010	30010	30010	9478767	0	49	96955	100035	100035	95885	0	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1894	18	16	17	10	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	1	1	0	2	68	91182	25	30010	30010	30010	9478767	1	49	96955	100035	100035	95885	0	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1894	18	16	16	16	99714	30000	30010	100036	100075	100036	100036	100036
30024	100035	750	1	1	9	2	638	91182	25	30010	30010	30105	9478767	0	49	96955	100035	100035	95885	0	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1894	18	16	17	18	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	1	1	0	2	68	91182	25	30010	30010	30010	9478767	0	49	96955	100035	100035	95885	0	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1894	15	16	17	18	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	1	1	0	2	68	91182	25	30010	30010	30010	9478767	0	49	96955	100035	100035	95885	0	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1894	16	16	16	15	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	1	1	0	2	733	91182	25	30010	30010	30010	9478767	0	49	93923	100035	100035	95885	0	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1894	15	16	16	21	99714	30000	30010	100036	100036	100036	100036	100036
30024	100035	749	1	1	0	2	311	91182	25	30010	30010	30010	9478767	1	49	96955	100035	100035	95885	0	3	96265	30010	30020	60020	100035	193	1	1	30021	10	9	10	30010	10	0	0	0	0	0	1894	16	16	15	8	99714	30000	30010	100036	100036	100036	100036	100036

Test 4: throughput

Count: 8

Code:

  sdiv w0, w8, w9
  sdiv w1, w8, w9
  sdiv w2, w8, w9
  sdiv w3, w8, w9
  sdiv w4, w8, w9
  sdiv w5, w8, w9
  sdiv w6, w8, w9
  sdiv w7, w8, w9

Initialization

  mov w8, #0x7fffffff
  mov w9, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	160039	1198	0	0	0	0	61	79950	25	80100	80100	80100	4399225	1	49	156959	0	160039	160039	149901	3	150023	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5110	3	16	1	1	159980	80000	80100	160040	160040	160040	160040	160040
80204	160039	1199	0	0	0	0	61	79950	25	80100	80100	80100	4399225	1	49	156959	0	160039	160039	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5110	1	16	1	1	159980	80000	80100	160040	160040	160040	160040	160040
80204	160039	1198	0	0	0	0	61	79950	25	80100	80100	80100	4399225	1	49	156959	0	160039	160039	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5110	1	16	1	1	159980	80000	80100	160040	160040	160040	160040	160040
80204	160039	1199	0	0	0	0	61	79950	25	80100	80100	80100	4399225	0	49	156959	0	160039	160039	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5110	1	16	1	1	159980	80000	80100	160040	160040	160040	160040	160040
80204	160039	1199	0	0	0	0	61	79950	25	80100	80100	80100	4399225	0	49	156959	0	160039	160039	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	1	0	5110	1	16	1	1	159980	80000	80100	160040	160040	160040	160040	160040
80204	160039	1198	0	0	0	0	61	79950	25	80100	80100	80100	4399225	0	49	156959	0	160039	160039	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5110	1	16	1	1	159980	80000	80100	160040	160040	160040	160040	160040
80204	160039	1198	0	0	0	0	61	79950	25	80100	80100	80100	4399225	0	49	156959	0	160039	160039	149940	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5110	1	16	1	1	159980	80000	80100	160040	160040	160040	160040	160040
80204	160039	1199	0	0	0	0	61	79950	25	80100	80100	80100	4399225	1	49	156959	0	160039	160039	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5110	1	16	1	1	159980	80000	80100	160040	160040	160040	160082	160040
80204	160039	1199	0	0	0	0	61	79950	25	80100	80100	80100	4399225	0	49	156959	0	160039	160039	149901	3	149997	80100	80200	160200	160039	526	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5110	1	16	1	1	159980	80000	80100	160040	160040	160040	160040	160040
80204	160039	1198	0	0	0	0	61	79950	25	80100	80100	80100	4399225	1	49	156959	0	160039	160039	149901	3	149997	80100	80200	160200	160039	261	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	5110	1	16	1	1	159980	80000	80100	160040	160040	160040	160040	160040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	19	1e	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	c2	cf	d0	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? int retires (ef)	f5	f6	f7	f8	fd
80024	160039	1199	1	1	0	0	2	1165	79950	25	80010	80010	80010	4398775	0	49	156959	0	160039	160039	149923	3	150019	80010	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	0	0	0	5023	0	19	16	0	16	16	159980	80000	0	0	80010	160040	160040	160040	160040	160040
80024	160039	1199	1	1	0	0	2	68	79950	25	80010	80010	80010	4398775	0	49	156959	0	160039	160039	149923	3	150019	80010	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	0	258	0	5023	0	16	16	0	8	15	159980	80000	0	0	80010	160040	160040	160040	160040	160040
80024	160039	1198	1	1	0	0	2	68	79950	25	80010	80010	80010	4398775	0	49	156959	0	160039	160039	149923	3	150019	80010	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	0	0	0	5023	0	14	16	0	15	15	159980	80000	0	0	80010	160040	160040	160040	160040	160040
80024	160039	1199	1	1	0	0	2	68	79950	25	80010	80010	80010	4398775	0	49	156959	0	160039	160039	149923	3	150019	80010	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	0	0	0	5023	0	16	16	0	16	16	159980	80000	0	0	80010	160040	160040	160040	160040	160040
80024	160039	1199	1	1	0	0	2	68	79950	25	80010	80010	80010	4398775	0	49	156959	0	160039	160039	149923	3	150019	80010	80020	160020	160039	526	1	1	80021	10	9	10	80010	10	0	3	0	5023	0	15	16	0	15	19	159980	80000	0	0	80010	160040	160040	160040	160040	160040
80024	160039	1199	1	1	0	0	2	733	79950	25	80010	80010	80010	4398775	0	49	156959	0	160039	160080	149923	3	150019	80010	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	0	0	0	5023	0	15	16	0	17	15	159980	80000	0	0	80010	160040	160040	160040	160040	160040
80024	160039	1198	1	1	0	0	2	68	79950	25	80010	80010	80010	4398775	0	49	156959	0	160039	160039	149923	3	150019	80010	80020	160020	160039	261	1	1	80022	10	9	10	80010	10	0	0	0	5023	0	12	16	0	9	15	159980	80000	0	0	80010	160040	160040	160040	160040	160040
80024	160039	1199	1	1	0	0	2	733	79950	25	80010	80010	80010	4398775	0	49	156959	0	160039	160039	149923	3	150019	80010	80020	160020	160078	261	1	1	80021	10	9	10	80010	10	0	0	0	5023	0	17	16	0	13	16	159980	80000	0	9	80010	160040	160040	160040	160040	160040
80024	160039	1199	1	1	0	0	2	68	79950	25	80010	80010	80010	4398775	0	49	156959	0	160039	160039	149923	3	150019	80010	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	0	0	0	5023	0	16	16	0	15	16	159980	80000	0	0	80010	160040	160040	160040	160040	160040
80024	160079	1199	1	1	0	0	2	68	79950	25	80010	80010	80010	4398775	0	49	156959	0	160039	160039	149923	3	150019	80010	80020	160020	160039	261	1	1	80021	10	9	10	80010	10	0	0	0	5023	0	19	57	0	15	16	160018	80000	0	0	80010	160040	160040	160040	160040	160040

SDIV (slow, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations