Firestorm: TBNZ (taken) measurements

Code:

  tbnz x0, #1, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	f5	f6	f7	f8	fd
1004	3898	6	0	35	25	1000	1000	1000	5000	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	0	73	2	21	1	1	532	536	536	536	536	536
1004	535	3	0	35	25	1000	1000	1000	5000	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	0	73	1	21	1	1	532	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	0	73	1	21	1	1	532	536	536	536	536	536
1004	535	4	51	35	25	1000	1000	1000	5000	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	0	73	1	21	1	1	532	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	0	73	1	21	1	1	532	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	0	73	1	21	1	1	532	536	536	536	536	536
1004	535	3	0	35	25	1000	1000	1000	5000	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	0	73	1	21	1	1	532	536	536	536	536	536
1004	535	4	3	35	25	1000	1000	1000	5000	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	0	73	1	21	1	1	532	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	0	73	1	21	1	1	532	536	536	536	536	536
1004	535	4	0	35	25	1000	1000	1000	5000	535	535	162	3	180	1000	1000	1000	535	535	1	1	1001	1000	0	73	1	21	1	1	532	536	536	536	536	536

Count: 8

Code:

  tbnz x0, #1, .+4
  tbnz x0, #1, .+4
  tbnz x0, #1, .+4
  tbnz x0, #1, .+4
  tbnz x0, #1, .+4
  tbnz x0, #1, .+4
  tbnz x0, #1, .+4
  tbnz x0, #1, .+4

Initialization

  mov x0, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0096

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int retires (ef)	f5	f6	f7	f8	fd
80205	81042	606	0	0	0	0	28	27	80105	80105	80107	400530	1	49	77680	80766	80768	6	10	80107	80207	80207	80778	64734	1	1	80201	80100	80099	100	100	100	0	0	0	0	1	1	1	80747	437	697	312	314	80761	100	80801	80773	80773	80771	80775
80204	80766	605	0	0	0	0	28	27	80105	80105	80107	400530	1	49	77692	80764	80766	6	10	80107	80207	80207	80764	64722	1	1	80201	80100	80099	100	100	100	0	0	0	0	1	1	1	80763	315	647	314	316	80767	100	80809	80797	80793	80787	80769
80204	80766	605	0	0	0	0	28	27	80105	80105	80107	400530	1	49	77692	80762	80766	6	10	80107	80207	80207	80762	64724	1	1	80201	80100	80099	100	100	100	0	0	0	0	1	1	1	80751	315	645	312	313	80765	100	80795	80795	80805	80807	80775
80204	80766	605	0	0	0	0	28	27	80105	80105	80107	400530	1	49	77714	80792	80792	6	10	80107	80207	80207	80792	64744	1	1	80201	80100	80099	100	100	100	0	0	0	0	1	1	1	80775	335	667	327	329	80791	100	80801	80767	80769	80765	80777
80204	80762	605	0	0	0	0	28	27	80105	80105	80107	400530	1	49	77696	80776	80782	6	10	80107	80207	80207	80776	64736	1	1	80201	80100	80099	100	100	100	0	0	0	0	1	1	1	80781	311	637	319	327	80783	100	80809	80789	80787	80785	80787
80204	80780	605	0	0	0	0	28	27	80105	80105	80107	400530	1	49	77696	80774	80772	6	10	80107	80207	80207	80780	64742	1	1	80201	80100	80099	100	100	100	4	0	0	0	1	1	1	80743	315	647	317	313	80761	100	80789	80793	80787	80783	80791
80204	80784	605	0	0	0	0	28	27	80105	80105	80107	400530	1	49	77686	80764	80766	6	10	80107	80207	80207	80762	64718	1	1	80201	80100	80099	100	100	100	0	0	0	0	1	1	1	80767	327	665	334	328	80783	100	80789	80771	80771	80765	80763
80204	80766	605	0	0	0	0	28	27	80105	80105	80107	400530	1	49	77698	80774	80778	6	10	80107	80207	80207	80776	64722	1	1	80201	80100	80099	100	100	100	0	0	0	0	1	1	1	80751	325	651	320	318	80769	100	80799	80797	80787	80795	80793
80204	80786	605	0	0	0	0	503	27	80105	80105	80107	400530	1	49	77692	80784	80784	6	10	80107	80207	80207	80804	64736	1	1	80201	80100	80099	100	100	100	0	0	0	0	1	1	1	80747	318	649	313	313	80761	100	80793	80775	80767	80767	80765
80204	80758	605	0	0	0	0	28	27	80105	80105	80107	400530	1	49	77702	80780	80772	39	10	80107	80207	80207	80770	64726	1	1	80201	80100	80099	100	100	100	0	0	0	0	1	1	1	80763	320	665	323	319	80777	100	80797	80771	80769	80759	80763

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 3.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	18	19	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	ea	ec	? int retires (ef)	f5	f6	f7	f8	fd
80024	240119	1798	0	0	0	0	0	1	35	28	80011	80011	80012	400058	0	0	49	236962	0	240042	240050	6	10	80012	80022	80022	240046	240048	1	1	80021	80010	80009	10	10	10	0	67	0	0	1	1	1	240022	0	0	79833	160014	0	79991	80002	240039	0	0	10	240043	240048	240044	240043	240045
80024	240042	1798	1	1	0	0	0	1	35	28	80011	80011	80012	400058	0	0	49	236960	0	240044	240042	18	10	80012	80022	80022	240044	240042	1	1	80021	80010	80009	10	10	10	0	0	0	0	1	1	1	240020	0	0	80002	160014	0	79992	80002	240041	0	0	10	240045	239996	240043	240041	240043
80024	240042	1798	1	1	0	0	0	1	35	28	80011	80011	80012	400058	0	0	49	236962	0	240044	240042	6	10	80054	80022	80022	240044	240044	1	1	80021	80010	80009	10	10	10	0	0	0	0	1	1	1	240020	0	0	80001	160012	0	79991	80002	240039	0	0	10	240043	240043	240043	240043	240045
80024	240044	1798	1	1	0	0	9	1	35	28	80011	80011	80012	400058	0	0	49	236960	0	240042	240042	6	10	80012	80093	80022	240044	240042	1	1	80021	80010	80009	10	10	10	0	0	0	0	1	1	1	240022	0	0	80002	160024	0	79991	80002	240041	0	0	10	240041	240043	240043	239916	240113
80024	240044	1798	1	1	0	0	0	1	35	28	80011	80011	80012	400058	0	0	49	236960	0	240044	240044	6	10	80012	80022	80073	240044	240044	1	1	80021	80010	80009	10	10	10	0	0	0	0	1	1	1	240021	9	1	80001	160014	0	79992	80003	240039	0	0	10	240043	240043	240043	240043	239910
80025	240042	1798	1	1	0	0	0	1	35	28	80011	80011	80012	400058	0	0	49	236962	0	240044	240040	6	10	80012	80022	80022	240099	240050	1	1	80021	80010	80009	10	10	10	0	0	0	0	1	1	1	240021	0	0	80002	160016	0	79992	80002	240041	0	0	10	240045	240043	240043	240045	240045
80024	240044	1798	1	1	0	0	0	1	35	28	80011	80011	80012	400058	0	0	49	236962	0	240044	240042	6	10	80012	80022	80022	240042	240044	1	1	80021	80010	80009	10	10	10	0	0	3	0	1	1	1	240021	0	0	80002	160014	0	79992	80002	240041	0	0	10	240045	240045	240043	240043	240045
80024	240044	1798	2	1	0	0	0	1	35	28	80011	80011	80012	400058	0	0	49	236962	0	240044	240042	6	10	80012	80022	80022	240042	240044	1	1	80021	80010	80009	10	10	10	0	0	0	0	1	1	1	240021	0	0	80002	160014	0	79992	80002	240041	0	0	10	240045	240043	240043	240043	240045
80024	240042	1797	1	2	0	0	0	1	700	28	80011	80011	80078	400058	0	0	49	236962	0	240044	240042	6	10	80012	80022	80022	240042	240042	1	1	80021	80010	80009	10	10	10	0	0	0	0	1	1	1	240021	0	0	80002	160014	0	79992	80003	240039	0	0	10	240045	240043	240041	240043	240043
80024	240042	1798	1	1	0	0	0	1	1568	28	80011	80011	80012	400058	0	0	49	236958	0	240046	240048	6	10	80012	80022	80022	240044	240042	1	1	80021	80010	80009	10	10	10	0	0	0	0	1	1	1	239968	5	0	80002	160014	0	79994	80003	240039	0	0	10	240047	240047	240051	240047	240043

TBNZ (taken)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations