Firestorm: PRFM (register, PSTL3KEEP) measurements

Code:

  prfm pstl3keep, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	92	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	1617	12	32	17	34	2442	1600	852	25	1000	1000	1000	69791	1	1571	1586	1316	3	1432	1000	1000	1000	1568	1574	1	1	1001	254	2265	2262	3298	0	2455	2305	1000	73	1	16	1	1	1517	1000	1615	1601	1615	1576	1579
1004	1629	12	32	18	34	2442	1553	878	25	1000	1000	1000	69999	1	1588	1574	1303	3	1429	1000	1000	1000	1595	1570	1	1	1001	235	2284	2242	3266	0	2452	2260	1000	73	1	16	1	1	1503	1000	1619	1587	1595	1610	1632
1004	1585	12	33	17	34	2466	1554	887	25	1000	1000	1000	70324	1	1583	1598	1307	3	1456	1000	1000	1000	1583	1594	1	1	1001	255	2281	2298	3256	0	2438	2270	1000	73	1	16	1	1	1477	1000	1575	1572	1616	1607	1572
1004	1576	12	32	18	34	2439	1585	895	25	1000	1000	1000	70472	1	1597	1606	1279	3	1465	1000	1000	1000	1576	1577	1	1	1001	253	2262	2300	3281	0	2466	2266	1000	73	1	16	1	1	1477	1000	1592	1591	1572	1614	1612
1004	1580	12	32	18	32	2434	1576	863	25	1000	1000	1000	69791	1	1590	1580	1315	3	1597	1000	1000	1000	1575	1569	1	1	1001	253	2278	2301	3243	0	2433	2272	1000	73	1	16	1	1	1496	1000	1616	1571	1627	1608	1611
1004	1624	12	32	18	35	2441	1584	869	25	1000	1000	1000	68353	1	1587	1626	1317	3	1450	1000	1000	1000	1589	1593	1	1	1001	221	2265	2251	3265	0	2447	2265	1000	73	1	16	1	1	1504	1000	1568	1593	1569	1574	1618
1004	1574	11	36	15	34	2470	1584	888	25	1000	1000	1000	69284	1	1578	1546	1287	3	1423	1000	1000	1000	1594	1566	1	1	1001	242	2263	2283	3271	0	2480	2269	1000	73	1	16	1	1	1495	1000	1566	1594	1568	1621	1586
1004	1614	12	33	17	34	2714	1570	890	25	1000	1000	1000	68750	1	1577	1579	1300	3	1472	1000	1000	1000	1588	1601	1	1	1001	247	2261	2272	3287	0	2475	2268	1000	73	1	16	1	1	1470	1000	1569	1619	1641	1595	1595
1004	1562	11	32	17	35	2457	1581	911	25	1041	1000	1000	68781	1	1554	1563	1281	3	1431	1000	1000	1000	1576	1581	1	1	1001	237	2250	2299	3278	0	2454	2279	1000	73	1	16	1	1	1490	1000	1612	1592	1599	1572	1598
1004	1568	12	34	16	33	2447	1599	890	25	1000	1000	1000	68653	1	1604	1592	1304	3	1471	1000	1000	1000	1572	1602	1	1	1001	258	2270	2288	3289	0	2427	2286	1000	73	1	16	1	1	1508	1000	1597	1610	1590	1600	1613

Test 2: throughput

Code:

  prfm pstl3keep, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5678

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	15816	120	360	189	348	0	0	24651	15982	9686	25	20223	10211	10000	10100	10000	132301	734570	1	40	49	12933	15524	15838	13000	3	13111	20100	10200	10000	10200	10000	15660	155	1	1	20201	100	99	2279	100	10100	100	23067	22717	32807	0	24548	22910	10000	0	1310	1	25	1	1	15748	10090	10000	10100	15592	15655	15703	15635	15839
20204	15866	116	358	192	359	1	1	25031	15651	9704	25	20199	10202	10000	10100	10000	131478	733243	1	43	49	12711	15664	15768	12931	3	13165	20100	10200	10000	10200	10000	15605	155	1	1	20201	100	99	2268	100	10100	100	23062	22815	32845	0	24763	22993	10000	0	1310	1	16	1	1	15618	10105	10000	10100	15563	15565	15699	15682	15603
20204	15678	117	353	191	350	0	0	24723	15610	9764	25	20190	10208	10000	10100	10000	130323	738703	1	37	49	12603	15585	15693	12981	3	13188	20100	10200	10000	10200	10000	15682	161	1	1	20201	100	99	2243	100	10100	100	22829	22805	32751	0	24528	22744	10000	0	1310	1	16	1	1	15611	10123	10000	10100	15619	15762	15616	15677	15753
20204	15699	116	359	187	348	0	0	24639	15608	9600	25	20217	10250	10000	10100	10000	132659	728464	1	40	49	12500	15758	15653	13007	3	13252	20100	10200	10000	10200	10000	15664	163	1	1	20201	100	99	2351	100	10100	100	22849	22941	32789	0	24440	22893	10000	0	1310	1	17	1	1	15657	10123	10000	10100	15659	15612	15603	15715	15626
20204	15697	117	349	187	350	0	0	24560	15589	9705	25	20223	10232	10000	10100	10000	131140	739593	1	35	49	12761	15662	15826	12888	3	13237	20100	10317	10000	10200	10000	15595	154	1	1	20201	100	99	2349	100	10100	100	22903	22948	32844	0	24645	22947	10000	0	1310	1	16	1	1	15506	10117	10000	10100	15718	15701	15631	15658	15610
20204	15649	117	350	191	347	0	0	24446	15589	9705	25	20205	10214	10000	10100	10000	132436	729945	1	35	49	12718	15548	15602	12960	3	13250	20100	10200	10000	10200	10000	15653	154	1	1	20201	100	99	2280	100	10100	100	23009	22773	32917	0	24560	22780	10000	0	1310	1	16	1	1	15545	10123	10000	10100	15608	15603	15746	15627	15766
20204	15714	118	355	191	355	0	0	24690	15639	9769	25	20172	10187	10000	10100	10000	132368	732605	1	33	49	12641	15721	15588	12892	3	13074	20100	10200	10000	10200	10000	15675	156	1	1	20201	100	99	2413	100	10100	100	23080	22817	32957	0	24368	23105	10000	0	1310	1	16	1	1	15484	10105	10000	10100	15714	15768	15616	15679	15742
20204	15717	117	357	197	349	0	0	24374	15600	9692	25	20215	10220	10000	10100	10000	133128	734428	1	38	49	12583	15699	15593	13044	3	13197	20100	10200	10000	10200	10000	15753	155	1	1	20201	100	99	2411	100	10100	100	22854	22799	32926	0	24537	22633	10000	0	1310	1	16	1	1	15603	10120	10000	10100	15701	15688	15546	15770	15659
20204	15781	118	347	194	359	0	0	24468	15688	9787	25	20199	10202	10000	10100	10000	131343	738703	1	31	49	12633	15629	15620	13017	3	13261	20100	10200	10000	10200	10000	15601	155	1	1	20201	100	99	2405	100	10100	100	22724	22885	32849	0	24636	22765	10000	0	1336	1	16	1	1	15556	10102	10000	10100	15664	15673	15618	15684	15551
20204	15682	118	349	189	354	0	0	24524	15816	9667	25	20214	10193	10000	10100	10000	132232	733944	1	37	49	12703	15700	15769	12956	3	13167	20100	10200	10000	10200	10000	15548	162	1	1	20201	100	99	2437	100	10100	100	22717	22861	32874	0	24654	22969	10000	0	1310	1	16	1	1	15550	10141	10000	10100	15782	15573	15576	15631	15739

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5479

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	15499	115	384	199	390	0	0	25167	0	0	15523	9518	25	20127	10139	10000	10010	10000	129643	717049	0	41	49	12413	15616	15468	12854	3	12935	20010	10020	10000	10020	10000	15556	146	1	1	20021	10	9	2082	10	10010	10	23513	23439	33472	0	25277	23522	10000	0	1270	1	16	2	1	15409	10129	10000	10010	15561	15425	15553	15398	15569
20024	15493	115	386	203	384	0	0	25245	0	0	15476	9443	25	20151	10145	10000	10010	10000	130476	723140	0	33	49	12327	15412	15429	12762	3	13018	20010	10020	10000	10020	10000	15416	154	1	1	20021	10	9	2080	10	10010	10	23401	23340	33286	0	25016	23534	10000	0	1270	1	16	1	1	15454	10105	10000	10010	15520	15573	15582	15484	15378
20024	15481	115	380	197	389	0	0	25125	0	0	15415	9575	25	20163	10157	10000	10010	10000	130058	727283	0	48	49	12386	15429	15441	12754	3	12880	20010	10020	10000	10020	10000	15485	146	1	1	20021	10	9	2071	10	10010	10	23277	23274	33303	0	25120	23185	10000	0	1271	1	16	1	1	15404	10132	10000	10010	15489	15473	15543	15354	15469
20024	15552	116	379	213	387	0	0	25015	0	0	15472	9473	25	20151	10130	10000	10010	10000	128907	721099	0	38	49	12204	15333	15452	12801	3	12996	20010	10020	10000	10020	10000	15329	141	1	1	20021	10	9	2189	10	10010	10	23438	23277	33514	0	25099	23326	10000	0	1270	1	16	1	1	15338	10117	10000	10010	15386	15497	15459	15671	15491
20024	15454	116	381	204	381	0	0	25233	0	0	15458	9626	25	20154	10142	10000	10010	10000	128860	725201	0	49	49	12294	15435	15424	12721	3	13034	20010	10020	10000	10020	10000	15417	151	1	1	20021	10	9	2016	10	10010	10	23315	23390	33349	0	25301	23340	10000	2	1270	1	16	1	1	15344	10147	10000	10010	15510	15486	15521	15448	15490
20024	15445	116	383	208	381	0	0	25002	0	0	15476	9423	25	20154	10154	10000	10010	10000	129992	720892	0	39	49	12530	15559	15493	12881	3	12851	20010	10020	10000	10020	10000	15475	153	1	1	20021	10	9	2088	10	10010	10	23449	23474	33407	0	25325	23513	10000	0	1270	1	16	1	1	15477	10135	10000	10010	15520	15409	15443	15293	15374
20024	15412	116	392	208	386	0	0	25407	0	0	15465	9498	25	20163	10160	10000	10010	10000	129362	732061	0	41	49	12472	15348	15494	12828	3	13042	20010	10020	10000	10020	10000	15471	140	1	1	20021	10	9	2069	10	10010	10	23171	23204	33268	0	24994	23285	10000	0	1270	1	15	1	1	15522	10123	10000	10010	15567	15416	15483	15489	15513
20024	15474	117	386	205	384	0	0	24999	0	0	15535	9528	25	20145	10148	10000	10010	10000	128375	728420	0	50	49	12284	15460	15506	12885	3	12868	20010	10020	10000	10020	10000	15435	144	1	1	20021	10	9	2084	10	10010	10	23413	23481	33431	0	25078	23505	10000	0	1270	1	16	1	1	15295	10129	10000	10010	15415	15596	15498	15392	15432
20024	15524	115	381	196	381	0	0	24926	0	1	15381	9434	25	20160	10133	10000	10010	10000	128317	722444	0	55	49	12308	15593	15506	12801	3	12940	20010	10020	10000	10020	10000	15344	144	1	1	20021	10	9	2139	10	10010	10	23454	23662	33285	0	25261	23428	10000	0	1270	1	16	1	1	15356	10120	10000	10010	15521	15584	15588	15416	15392
20024	15348	115	383	202	385	0	0	24928	0	0	15564	9505	25	20130	10166	10000	10010	10000	130408	723785	0	36	49	12443	15442	15548	12794	3	12883	20010	10020	10000	10141	10000	15652	147	1	1	20021	10	9	2038	10	10010	10	23216	23427	33573	0	25332	23524	10000	0	1270	1	15	1	1	15430	10123	10000	10010	15423	15427	15483	15442	15548

Test 3: throughput

Code:

  prfm pstl3keep, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5378

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10204	15402	115	0	353	186	349	24787	0	15332	9331	25	10100	100	10000	100	10000	500	719588	0	49	12384	15381	15392	13951	7	14056	10100	200	10016	200	10016	15303	12117	1	1	10201	100	99	2492	100	100	100	22782	22880	32890	2	24679	22875	10000	0	1	1	1	718	0	16	0	15286	10000	100	15411	15347	15430	15501	15436
10204	15362	116	0	347	184	357	24739	108	15402	9342	25	10100	100	10000	100	10002	500	726118	0	49	12259	15346	15378	13883	6	14180	10100	200	10008	200	10008	15311	12141	1	1	10201	100	99	2483	100	100	100	22864	22868	32984	0	24549	22938	10000	0	1	1	1	719	0	16	0	15238	10000	100	15347	15493	15442	15361	15396
10204	15334	115	0	352	186	348	24600	0	15249	9380	25	10100	100	10000	100	10000	500	724636	0	49	12264	15416	15314	13946	6	14147	10103	200	10016	200	10008	15363	12126	1	1	10201	100	99	2460	100	100	100	22880	22881	32917	0	24705	22874	10000	0	1	1	1	717	0	16	0	15338	10000	100	15373	15362	15349	15301	15411
10204	15403	114	1	345	182	349	24645	0	15513	9471	25	10100	100	10000	100	10000	500	720689	0	49	12276	15404	15346	13943	6	14058	10100	200	10008	200	10008	15386	12252	1	1	10201	100	99	2538	100	100	100	22956	22932	32979	0	24680	22854	10000	0	1	1	1	719	0	16	0	15368	10000	100	15368	15394	15454	15445	15406
10204	15485	116	0	346	191	347	24669	0	15437	9359	25	10100	100	10000	100	10000	500	724337	0	49	12311	15479	15400	13910	7	14054	10100	200	10008	200	10008	15369	12196	1	1	10201	100	99	2506	100	100	100	22928	23099	32865	12	24770	22798	10000	0	1	1	1	718	0	16	0	15354	10000	100	15373	15477	15460	15350	15405
10204	15469	116	0	347	183	348	24728	0	15390	9341	25	10100	100	10000	100	10000	500	719592	0	49	12236	15461	15337	13863	7	14108	10100	200	10008	200	10016	15404	12174	1	1	10201	100	99	2549	100	100	100	22927	22898	32931	0	24752	22904	10000	0	1	1	1	717	0	16	0	15242	10000	100	15391	15359	15340	15420	15464
10204	15422	115	0	345	180	346	24715	0	15461	9413	25	10100	100	10000	100	10002	500	717822	1	49	12367	15419	15422	13892	6	14147	10100	200	10024	200	10016	15338	12142	1	1	10201	100	99	2510	100	100	100	23001	22936	32891	0	24636	22888	10000	0	1	1	1	718	0	16	0	15288	10000	100	15413	15372	15361	15327	15454
10204	15524	115	0	344	191	344	24689	0	15402	9328	25	10100	100	10000	100	10001	500	719501	0	49	12304	15344	15340	13998	7	14012	10100	200	10016	200	10016	15375	12151	1	1	10201	100	99	2436	100	100	100	22792	22913	33002	0	24638	22871	10000	0	1	1	1	717	0	16	0	15347	10000	100	15460	15398	15338	15431	15481
10204	15428	116	0	347	181	350	24745	0	15375	9463	25	10100	100	10000	100	10010	500	721667	0	49	12257	15301	15330	13934	6	14099	10107	200	10016	200	10016	15363	12184	1	1	10201	100	99	2518	100	100	100	22947	22967	32969	0	24680	22935	10000	0	1	1	1	717	0	16	0	15280	10000	100	15366	15432	15361	15491	15385
10204	15287	115	0	352	188	350	24695	0	15376	9439	25	10100	100	10000	100	10000	500	722313	0	49	12312	15380	15393	13988	6	14069	10100	200	10008	200	10016	15377	12084	1	1	10201	100	99	2442	100	100	100	22978	22911	32914	5	24744	22817	10000	0	1	1	1	718	0	16	0	15302	10000	100	15363	15419	15431	15378	15343

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5568

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10024	15631	116	295	148	296	23991	15600	9617	25	10010	10	10000	10	10000	50	726400	0	49	12469	15557	15636	14216	3	14313	10010	20	10000	20	10000	15557	15521	1	1	10021	10	9	2739	10	10	10	22198	22327	32311	0	24013	22332	10000	0	640	2	16	2	2	15440	10000	10	15608	15493	15585	15597	15567
10024	15601	117	296	149	296	24038	15553	9605	25	10010	10	10000	10	10000	50	727287	1	49	12499	15534	15529	14148	3	14366	10010	20	10000	20	10000	15475	15485	1	1	10021	10	9	2712	10	10	10	22318	22329	32257	0	24100	22309	10000	0	640	2	16	2	2	15484	10000	10	15549	15572	15513	15486	15522
10024	15485	117	294	147	294	23932	15619	9692	25	10010	10	10067	10	10000	50	728600	1	49	12527	15533	15534	14156	3	14290	10010	20	10000	20	10000	15519	15520	1	1	10021	10	9	2731	10	10	10	22214	22233	32329	0	24038	22290	10000	0	640	2	17	2	2	15509	10000	10	15514	15625	15580	15571	15541
10024	15583	116	297	146	295	23958	15575	9726	25	10010	10	10000	10	10000	50	731680	0	49	12498	15628	15622	14217	3	14226	10010	20	10000	20	10000	15602	15538	1	1	10021	10	9	2743	10	10	10	22274	22285	32334	4	24010	22264	10000	0	640	2	16	2	2	15414	10000	10	15574	15583	15582	15523	15579
10024	15581	116	293	147	299	24005	15608	9630	25	10010	10	10000	10	10000	50	730025	1	49	12541	15534	15612	14108	3	14257	10010	20	10000	20	10000	15506	15556	1	1	10021	10	9	2729	10	10	10	22254	22195	32239	21	24013	22252	10000	0	640	2	16	2	2	15444	10000	10	15552	15609	15577	15646	15570
10024	15577	116	297	149	296	23997	15544	9689	25	10010	10	10000	10	10000	50	727166	1	49	12503	15471	15678	14136	3	14378	10010	20	10000	20	10000	15555	15487	1	1	10021	10	9	2739	10	10	10	22277	22279	32283	0	23990	22303	10000	0	640	2	16	2	2	15381	10000	10	15640	15597	15616	15523	15544
10024	15548	116	293	147	297	23880	15628	9619	25	10010	10	10000	10	10000	50	730110	0	49	12418	15650	15538	14187	3	14294	10010	20	10000	20	10000	15529	15517	1	1	10021	10	9	2676	10	10	10	22288	22283	32277	0	24073	22327	10000	0	640	2	16	2	2	15396	10000	10	15477	15600	15627	15569	15612
10024	15503	117	294	149	295	23938	15658	9551	25	10010	10	10000	10	10000	50	730922	1	49	12554	15578	15570	14196	3	14317	10010	20	10000	20	10000	15577	15569	1	1	10021	10	9	2649	10	10	10	22237	22295	32289	4	24279	22262	10000	0	640	2	16	2	2	15422	10000	10	15541	15565	15513	15547	15577
10024	15632	116	296	147	295	24008	15499	9546	25	10010	10	10000	10	10000	50	725564	0	49	12458	15605	15564	14136	3	14272	10010	20	10000	20	10000	15455	15485	1	1	10021	10	9	2640	10	10	10	22324	22287	32288	0	24015	22254	10000	0	640	2	16	2	2	15391	10000	10	15547	15574	15537	15528	15586
10024	15479	116	293	146	295	23967	15589	9603	25	10010	10	10000	10	10000	50	726296	1	49	12567	15554	15573	14159	3	14209	10010	20	10000	20	10000	15536	15586	1	1	10021	10	9	2711	10	10	10	22288	22273	32272	0	24067	22345	10000	0	640	2	16	2	2	15399	10000	10	15486	15503	15593	15529	15502

PRFM (register, PSTL3KEEP)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations