Firestorm: LDRSB (register, 64-bit) measurements

Code:

  ldrsb x0, [x6, x7]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	92	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	408	3	1	0	1	0	0	81	1	0	2	388	16	7	7	20	25	1000	1000	1000	15480	0	386	403	211	3	266	1000	1000	2000	408	85	1	1	1001	4	1000	1000	0	1020	19	58	1073	1	0	1	76	1015	6	1	59	43	19	2	73	1	16	1	1	405	10	0	0	1000	387	409	404	387	404
1004	408	3	1	0	0	0	0	81	0	0	3	387	23	0	7	4	25	1000	1000	1000	15526	1	389	388	225	3	266	1000	1000	2000	386	69	1	1	1001	4	1000	1000	0	1019	19	58	1034	0	0	0	60	1039	6	1	73	45	19	1	73	1	16	1	1	383	13	0	5	1000	409	410	409	404	409
1004	386	3	1	0	0	0	0	82	0	0	2	388	3	0	20	4	25	1000	1000	1000	15799	0	410	386	209	3	261	1000	1000	2000	403	69	1	1	1001	4	1000	1000	0	1020	20	43	1060	0	0	1	75	1023	0	1	34	43	19	1	73	1	16	1	1	405	0	13	5	1000	387	387	403	403	409
1004	403	3	1	0	1	0	0	36	1	0	2	393	2	0	20	4	25	1000	1000	1000	14843	0	386	408	209	3	261	1000	1000	2000	408	85	1	1	1001	0	1000	1000	0	1019	19	58	1034	0	0	0	60	1023	6	1	59	43	19	0	73	1	16	1	1	405	0	13	0	1000	387	387	403	410	404
1004	386	3	1	0	1	0	0	36	1	0	1	393	15	7	0	25	25	1000	1000	1000	15741	0	404	387	211	3	266	1000	1000	2000	408	85	1	1	1001	0	1000	1000	0	1020	20	58	1042	1	0	0	39	1054	6	1	59	43	19	2	73	1	16	1	1	383	0	13	5	1000	409	404	404	409	403
1004	403	3	1	0	0	0	0	66	1	0	2	388	16	7	0	25	25	1000	1000	1000	15799	0	403	386	231	3	247	1000	1000	2000	408	85	1	1	1001	4	1000	1000	0	1019	20	0	1042	1	0	0	44	1054	6	0	34	45	19	0	73	1	16	1	1	386	10	10	5	1000	409	409	387	409	390
1004	386	3	1	1	1	0	0	82	1	0	2	388	3	7	20	7	25	1000	1000	1000	15788	0	408	403	225	3	244	1000	1000	2000	386	68	1	1	1001	0	1000	1000	0	1019	19	45	1058	0	0	0	76	1055	0	0	59	43	19	1	73	1	16	1	1	405	0	0	0	1000	409	403	404	404	387
1004	403	3	1	0	1	0	0	67	1	0	2	371	15	7	20	20	25	1000	1000	1000	15480	0	386	408	225	3	261	1000	1000	2000	402	85	1	1	1001	4	1000	1000	0	1019	19	43	1074	0	0	0	61	1054	6	1	74	0	19	0	73	1	16	1	1	405	0	0	0	1000	409	387	409	404	387
1004	403	2	1	0	0	0	0	81	0	0	2	393	3	7	7	25	25	1000	1000	1000	14769	0	386	389	225	3	266	1000	1000	2000	408	91	1	1	1001	0	1000	1000	0	1019	20	43	1059	1	0	2	44	1040	6	1	58	0	19	0	73	1	16	1	1	386	10	10	5	1000	387	404	403	409	404
1004	408	3	1	1	1	0	0	82	1	0	1	389	16	7	0	25	25	1000	1000	1000	15526	0	408	408	225	3	247	1000	1000	2000	403	85	1	1	1001	0	1000	1000	0	1021	21	0	1073	1	0	0	60	1055	6	0	73	43	19	0	73	1	16	1	1	400	13	10	5	1000	409	409	404	387	409

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb x0, [x6, x7]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	19	1e	1f	22	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70057	525	1	1	0	1	0	1	70036	69782	59710	25	40104	30103	10001	30100	10000	616967	3342446	0	49	66971	70051	70051	64647	3	64954	40100	30200	10055	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	2611	3	71	3	3	69814	30003	10	10	10	10000	30100	70052	70052	70052	70052	70052
40204	70035	525	1	0	0	1	0	1	70036	69782	59710	25	40104	30103	10001	30100	10000	616878	3344414	0	49	66973	70051	70051	64631	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	2611	3	71	3	3	69798	30003	10	10	0	10000	30100	70052	70052	70052	70052	70052
40204	70051	525	0	0	0	1	0	0	70093	69782	59710	25	40104	30103	10001	30100	10000	616797	3344030	0	49	66971	70051	70051	64631	3	64938	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	2611	2	71	2	3	69814	30003	10	10	10	10000	30100	70052	70052	70052	70052	70052
40204	70051	525	0	0	0	1	0	0	70036	69782	59710	25	40104	30100	10001	30100	10000	616032	3344942	0	49	67313	70051	70051	64631	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	0	1	2611	3	71	3	3	69814	30000	10	10	10	10000	30100	70052	70052	70036	70052	70052
40204	70051	524	0	0	0	1	0	1	70036	69782	59710	25	40100	30103	10001	30100	10000	617057	3345278	0	49	66971	70051	70051	64631	3	64954	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	2611	3	71	3	3	69814	30003	10	10	10	10000	30100	70052	70052	70052	70052	70052
40204	70051	524	0	0	0	1	0	0	70036	69782	59710	25	40104	30103	10001	30100	10000	616175	3346366	0	49	66971	70051	70051	64647	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	2611	3	71	3	2	69814	30003	10	10	0	10000	30100	70052	70036	70052	70052	70036
40204	70051	525	0	0	0	1	0	1	70037	69782	59710	25	40104	30103	10001	30100	10000	616790	3342926	0	49	66971	70051	70035	64647	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	10000	1	1	2611	3	71	3	3	69814	30000	10	10	0	10000	30100	70036	70052	70052	70052	70052
40204	70035	524	0	0	0	0	0	1	70036	69782	59710	25	40100	30103	10001	30100	10000	616842	3345134	0	49	66955	70051	70051	64693	3	64961	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	5	3	10000	0	0	2611	3	71	2	3	69798	30003	10	10	10	10000	30100	70052	70052	70052	70052	70036
40204	70051	525	0	0	0	1	0	1	70036	69782	59695	25	40104	30103	10000	30100	10000	616860	3344558	0	49	66955	70051	70051	64647	3	64954	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	2611	3	71	3	2	69798	30003	10	0	10	10000	30100	70052	70052	70052	70052	70036
40204	70051	525	0	0	0	1	0	1	70036	69782	59710	25	40104	30100	10001	30100	10000	616842	3344606	0	98	66971	70035	70051	64631	3	64954	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	10000	1	1	2611	2	71	3	3	69814	30003	10	10	10	10000	30100	70052	70052	70052	70052	70052

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	cd	cf	d0	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70060	525	0	0	0	1	0	0	0	0	70039	69780	59713	25	40014	30013	10001	30010	10000	617018	3342398	0	49	66974	70035	70054	64672	0	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	10000	1	0	0	0	0	2520	0	0	1	71	0	1	1	69798	30003	13	10	13	10000	30010	70036	70036	70055	70055	70056
40024	70035	524	0	0	0	1	0	1	1	0	70020	69743	59713	25	40014	30013	10004	30010	10000	616991	3341566	1	49	66974	70054	70035	64672	0	3	64979	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	10000	1	0	0	0	0	2520	0	0	1	71	0	1	1	69817	30000	0	13	0	10000	30010	70055	70036	70055	70055	70055
40024	70054	525	0	0	0	0	0	1	1	0	70313	69756	60098	25	40014	30013	10001	30010	10000	617018	3342398	1	49	66974	70035	70055	64669	0	3	64960	40010	30020	10000	60354	20000	70054	35	2	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	0	10000	0	0	0	0	0	2520	0	0	1	71	0	1	1	69817	30003	13	13	0	10000	30010	70055	70052	70036	70055	70052
40024	70035	525	0	0	0	0	0	1	0	0	70039	69743	59695	25	40010	30013	10001	30010	10000	617018	3342398	0	49	66974	70035	70035	64672	7	3	64979	40010	30020	10000	60020	20000	70054	35	2	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	10000	1	1	0	0	0	2520	0	0	1	71	0	1	1	69843	30000	13	10	13	10000	30010	70036	70060	70052	70055	70055
40024	70054	525	0	0	0	0	0	1	0	0	70039	69778	59713	25	40010	30013	10000	30010	10000	617068	3341470	0	49	66974	70054	70035	64672	0	3	64979	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	0	10000	1	1	0	0	0	2520	0	0	1	71	0	1	1	69819	30003	10	0	0	10000	30010	70055	70098	70163	70055	70055
40024	70051	525	0	0	0	0	0	1	0	0	70020	69775	59713	25	40014	30013	10001	30010	10000	617018	3342398	0	49	66974	70054	70051	64653	0	3	64960	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	0	0	2520	0	0	1	71	0	1	2	69830	30000	10	0	10	10000	30010	70055	70036	70036	70055	70036
40024	70054	525	0	0	0	0	0	0	0	0	70039	69778	59713	25	40014	30010	10000	30010	10000	617018	3342398	1	49	66974	70054	70054	64672	0	3	64976	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	0	1	0	0	0	2520	0	0	1	71	0	1	1	69889	30003	0	0	13	10000	30010	70055	70036	70055	70055	70052
40024	70051	525	0	0	0	0	0	1	0	0	70036	69743	59713	25	40010	30013	10001	30010	10000	617018	3342398	0	49	66974	70054	70051	64669	0	3	64979	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	0	0	2520	0	0	1	71	0	2	1	69827	30003	10	10	13	10000	30010	70055	70055	70055	70036	70055
40024	70054	524	0	0	0	0	0	0	0	0	70039	69778	59713	25	40010	30013	10001	30010	10000	617018	3342398	0	49	66955	70051	70054	64653	0	3	64979	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	0	0	2520	0	0	1	71	0	1	1	69836	30003	10	13	13	10000	30010	70036	70052	70055	70036	70052
40024	70051	524	0	0	0	0	0	1	1	0	70020	69778	59710	25	40014	30013	10000	30010	10000	617018	3342398	0	49	66974	70054	70054	64672	0	3	64979	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	1	0	0	0	2520	0	0	1	71	0	1	1	69877	30003	10	0	13	10000	30010	70036	70055	70055	70036	70055

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb x0, [x6, x7]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0056

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	19	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70053	525	1	0	0	1	1	0	14	0	1	0	1	70050	69784	59790	25	40104	30103	10002	30100	10000	616175	3342206	1	49	66955	0	70035	70050	64631	3	64950	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	2	1	10001	1	1	1	10000	1	1	0	1	0	0	0	2610	1	71	1	1	69819	30003	9	0	0	10000	30100	70057	70054	70057	70059	70057
40204	70056	525	1	0	1	0	0	3	2	108	1	0	0	70043	69878	59717	25	40148	30165	10007	30264	10110	616059	3342494	0	49	66976	0	70041	70056	64652	3	64944	40100	30200	10000	60200	20000	70056	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	0	10001	0	0	1	10000	0	1	0	1	1	0	0	2610	1	71	1	1	69804	30003	6	6	9	10000	30100	70057	70042	70054	70044	70054
40204	70056	525	1	1	0	0	0	0	1	0	1	0	0	70041	69787	59774	25	40108	30106	10002	30100	10000	616059	3342542	0	49	66976	0	70041	70041	64652	3	64944	40100	30200	10000	60200	20000	70421	35	5	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	0	10000	2	0	0	10000	1	0	1	0	0	0	0	2610	1	71	1	0	69810	30003	0	9	9	10000	30100	70051	70036	70054	70116	70042
40204	70041	525	1	0	0	0	0	0	1	0	0	0	0	70041	69787	59871	25	40141	30106	10002	30100	10000	616059	3342494	0	49	66976	0	70288	70156	64637	3	64959	40100	30200	10000	60200	20000	70056	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	1	10002	1	0	1	10000	1	1	1	1	0	0	0	2610	1	71	1	1	69819	30006	9	6	0	10000	30100	70057	70057	70054	70099	70057
40204	70056	525	1	1	1	0	0	0	2	0	0	0	0	70026	69847	59767	25	40108	30106	10002	30100	10000	616059	3341769	0	49	66976	0	70056	70056	64637	3	64959	40100	30397	10000	60200	20000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	0	10002	1	2	1	10000	1	1	1	1	1	0	0	2645	1	71	1	1	69822	30003	9	6	0	10000	30100	70057	70042	70042	70057	70063
40204	70041	525	1	0	1	0	0	0	1	0	0	0	0	70026	69877	59717	25	40108	30106	10001	30100	10000	616059	3341769	0	49	66976	0	70041	70056	64652	3	64959	40100	30200	10000	60200	20000	70056	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10003	1	0	10002	0	0	1	10000	1	1	1	1	2	0	0	2610	1	71	1	1	69819	30006	9	9	9	10000	30100	70057	70042	70054	70145	70057
40204	70056	524	1	1	1	0	0	0	7	0	0	0	0	70026	69784	59748	25	40108	30106	10001	30100	10000	616078	3342494	0	49	66976	0	70056	70056	64652	3	64959	40100	30200	10000	60200	20000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	1	1	10001	0	1	1	10000	1	1	0	1	0	0	0	2610	1	71	1	1	69819	30006	9	9	9	10000	30100	70057	70054	70057	70085	70057
40204	70061	525	1	0	1	0	0	0	2	0	0	0	1	70041	69787	59715	25	40108	30106	10002	30100	10000	616059	3341769	0	49	66976	0	70056	70056	64652	3	64959	40100	30200	10000	60200	20000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	1	10002	0	0	1	10000	1	1	1	1	0	0	0	2610	1	71	1	1	69816	30006	9	0	9	10000	30100	70042	70042	70054	70057	70057
40204	70056	525	1	0	0	0	0	0	7	0	1	0	0	70105	69787	59715	25	40108	30106	10002	30100	10000	616078	3342350	0	49	66973	0	70109	70041	64652	3	64956	40100	30200	10000	60200	20000	70056	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	1	10002	1	1	1	10000	1	1	1	1	0	0	0	2610	1	71	1	1	69819	30006	9	9	9	10000	30100	70042	70057	70057	70057	70057
40204	70056	525	1	0	0	1	0	0	2	0	0	0	0	70041	69787	59715	25	40108	30106	10004	30100	10000	616059	3342494	0	49	66973	0	70056	70053	64649	3	64959	40100	30200	10000	60200	20000	70056	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	1	10001	0	2	7	10000	1	1	1	1	0	0	0	2610	1	71	1	1	69819	30006	9	0	9	10000	30100	70042	70057	70042	70057	70057

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0060

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	1e	1f	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70041	524	1	1	1	1	0	0	1	0	1	0	0	70045	69784	59701	25	40014	30013	10002	30010	10000	617063	3342542	49	66980	70060	70062	64678	3	64982	40010	30020	10000	60020	20000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	0	0	2520	2	71	2	2	69820	30003	10	10	0	10000	30010	70061	70061	70042	70058	70061
40024	70041	524	1	0	0	0	0	0	2	0	1	0	0	70042	69784	59719	25	40018	30016	10005	30155	10000	617072	3342686	49	66961	70057	70060	64659	3	64967	40010	30020	10000	60020	20000	70060	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	2	0	10001	0	0	1	10000	0	1	1	1	0	0	1	2520	5	71	4	2	69823	30003	13	0	0	10000	30010	70061	70061	70128	70055	70061
40024	70057	525	1	0	0	1	0	0	7	0	1	0	0	70045	69784	59719	25	40018	30016	10001	30010	10000	617072	3342686	49	66980	70060	70060	64659	3	65042	40010	30020	10000	60020	20000	70060	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	2	1	10001	0	1	1	10000	1	1	1	1	2	0	0	2520	5	71	3	2	69823	30006	13	11	13	10000	30010	70061	70042	70061	70061	70061
40024	70060	524	1	0	0	1	0	0	2	0	1	0	0	70045	69784	59716	25	40018	30016	10001	30010	10000	616995	3341769	49	66980	70060	70060	64659	3	65072	40010	30020	10000	60020	20000	70060	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10001	0	0	1	10000	0	1	1	1	0	0	0	2520	4	71	2	2	69804	30003	13	13	0	10000	30010	70058	70061	70058	70042	70058
40024	70060	525	1	0	0	0	1	0	2	0	1	0	0	70045	69784	59719	25	40018	30013	10002	30010	10000	617072	3342686	49	66980	70041	70060	64678	3	65055	40010	30020	10000	60020	20000	70060	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10002	0	0	1	10000	1	1	0	1	0	0	0	2520	2	71	3	2	69823	30003	0	10	0	10000	30010	70061	70061	70061	70061	70061
40024	70060	525	1	0	0	0	0	0	11	0	0	0	0	70045	69784	59695	25	40018	30013	10002	30010	10000	616995	3342686	49	66961	70041	70060	64678	3	65017	40010	30020	10000	60020	20000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10001	1	1	10001	0	1	1	10000	0	1	1	1	0	0	0	2520	2	71	3	4	69804	30006	13	0	13	10000	30010	70042	70058	70061	70061	70058
40024	70060	524	1	1	1	1	0	0	1	0	1	0	0	70045	69789	59719	51	40018	30013	10002	30010	10000	617072	3342686	49	66980	70060	70060	64659	3	65019	40010	30020	10000	60020	20000	70060	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10003	1	1	10002	0	0	1	10000	0	1	0	1	1	0	0	2520	2	71	2	2	69823	30006	10	13	13	10000	30010	70042	70042	70061	70061	70061
40024	70060	525	1	1	1	0	0	0	2	0	0	0	0	70045	69784	59719	25	40018	30016	10001	30010	10000	617144	3341817	49	66961	70060	70057	64678	3	65058	40010	30020	10000	60020	20000	70041	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	1	1	10001	0	1	1	10000	1	1	1	1	0	0	0	2520	2	71	2	2	69823	30006	10	13	10	10000	30010	70042	70061	70061	70042	70061
40024	70041	525	1	0	1	1	0	0	2	0	1	0	0	70045	69702	59719	25	40018	30016	10002	30010	10000	616995	3341769	49	66977	70060	70057	64678	3	65066	40010	30020	10000	60020	20000	70057	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	1	1	10002	0	1	1	10000	1	1	1	1	1	0	0	2520	2	71	4	4	69823	30006	13	0	0	10000	30010	70061	70061	70061	70061	70061
40024	70057	524	1	1	0	1	0	0	2	0	0	0	0	70045	69784	59701	25	40014	30016	10002	30010	10000	617072	3341769	49	66980	70060	70060	64675	3	65022	40010	30020	10000	60020	20000	70060	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10002	1	1	10001	0	1	1	10000	1	1	1	1	1	0	0	2520	3	71	2	2	69823	30006	10	13	13	10000	30010	70061	70061	70061	70061	70042

Test 4: throughput

Count: 8

Code:

  ldrsb x0, [x6, x7]
  ldrsb x0, [x6, x7]
  ldrsb x0, [x6, x7]
  ldrsb x0, [x6, x7]
  ldrsb x0, [x6, x7]
  ldrsb x0, [x6, x7]
  ldrsb x0, [x6, x7]
  ldrsb x0, [x6, x7]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26733	200	1	0	1	1	1	65	1	0	2	26724	2	18	18	15	25	80100	100	80000	100	80016	500	1169563	0	49	23634	26732	26733	16659	6	16685	80114	200	80024	200	160048	26732	81	1	1	80201	100	99	100	80000	100	80000	1	100	80020	20	42	80057	1	0	1	59	80038	6	1	56	42	19	1	1	1	1	5118	0	16	0	26730	9	9	2	80000	100	26733	26733	26733	26734	26733
80204	26732	200	1	0	1	0	1	65	0	0	2	26808	2	18	18	15	25	80100	100	80000	100	80016	500	1169757	0	49	23634	26732	26732	16660	6	16684	80115	200	80024	200	160048	26732	82	1	1	80201	100	99	100	80000	100	80000	0	100	80019	20	42	80056	1	0	1	59	80037	6	1	57	42	19	1	1	1	1	5118	0	16	0	26729	9	9	2	80000	100	26733	26733	26734	26733	26734
80204	26714	200	1	1	0	0	0	65	1	0	2	26724	2	18	18	0	25	80100	100	80000	100	80016	500	1167107	0	49	23652	26732	26733	16660	6	16684	80114	200	80024	200	160048	26732	81	1	1	80201	100	99	100	80000	100	80000	0	100	80020	19	42	80057	1	0	0	21	80000	6	1	57	42	19	2	1	1	1	5118	0	16	0	26730	9	9	2	80000	100	26733	26733	26733	26733	26733
80204	26732	201	1	1	1	0	0	65	0	0	2	26706	2	18	0	16	25	80100	100	80000	100	80016	500	1169563	1	49	23652	26714	26714	16660	6	16685	80118	200	80024	200	160048	26733	81	1	1	80201	100	99	100	80000	100	80000	0	100	80019	21	42	80057	1	0	0	59	80039	6	0	57	42	19	2	1	1	1	5118	0	16	0	26729	9	9	2	80000	100	26715	26715	26733	26733	26733
80204	26732	200	1	1	1	0	0	65	0	0	2	26699	2	18	18	17	25	80100	100	80000	100	80015	500	1166836	1	49	23652	26714	26715	16659	6	16683	80116	200	80024	200	160048	26732	64	1	1	80201	100	99	100	80000	100	80000	1	100	80019	20	41	80057	1	0	1	58	80168	6	1	56	42	19	2	1	1	1	5118	0	16	0	26729	9	9	2	80000	100	26733	26733	26733	26733	26734
80204	26733	200	1	0	1	0	0	65	0	0	2	26809	2	18	18	0	25	80100	100	80000	100	80016	500	1167763	0	49	23652	26732	26714	16660	6	16684	80116	200	80024	200	160048	26732	81	1	1	80201	100	99	100	80000	100	80000	0	100	80021	20	42	80057	1	0	0	59	80038	6	1	57	0	19	2	1	1	1	5118	0	16	0	26730	9	0	2	80000	100	26734	26733	26733	26733	26715
80204	26732	200	1	1	0	0	0	66	1	0	2	26712	2	12	12	16	25	80100	100	80000	100	80015	500	1167303	0	49	23647	26727	26727	16655	6	16662	80115	200	80024	202	160048	26736	71	1	1	80201	100	99	100	80000	100	80000	0	100	80000	0	39	80039	0	0	0	39	80039	6	1	39	39	0	0	1	1	1	5118	1	16	0	26724	10	6	4	80000	100	26728	26728	26728	26728	26728
80204	26727	200	0	0	0	0	0	41	1	0	1	26803	2	18	0	0	25	80100	100	80000	100	80014	500	1167875	0	49	23655	26745	26732	16660	6	16685	80112	200	80024	200	160048	26732	81	1	1	80201	100	99	100	80000	100	80000	1	100	80020	19	0	80057	1	0	1	60	80038	6	1	56	0	19	0	1	1	1	5118	0	16	0	26730	9	9	2	80000	100	26733	26733	26733	26734	26733
80204	26732	200	1	1	1	0	0	65	1	0	2	26725	2	18	18	16	25	80100	100	80000	100	80015	500	1167462	1	49	23653	26732	26732	16660	6	16684	80116	200	80024	200	160048	26732	64	1	1	80201	100	99	100	80000	100	80000	0	100	80019	20	42	80055	1	0	1	62	80038	6	1	57	42	19	0	1	1	1	5118	0	16	0	26730	9	9	2	80000	100	26733	26715	26734	26734	26733
80204	26733	200	1	1	0	0	1	65	0	0	2	26720	2	0	18	15	25	80100	100	80000	100	80016	500	1167095	1	49	23652	26732	26732	16660	6	16685	80115	200	80024	200	160048	26714	81	1	1	80201	100	99	100	80000	100	80000	0	100	80019	20	42	80019	1	0	0	59	80038	6	0	57	42	19	0	1	1	1	5118	0	16	0	26729	9	9	2	80000	100	26733	26733	26733	26733	26734

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	19	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26736	200	0	1	0	0	1	0	0	0	66	1	0	3	26721	3	9	7	0	25	80010	10	80000	10	80000	50	1173975	1	49	23635	26737	26737	16681	3	16784	80010	20	80000	20	160000	26736	85	1	1	80021	10	9	10	80000	10	80000	1	10	80020	19	43	0	80059	1	0	1	60	80039	6	1	58	43	19	1	5021	1	15	16	0	17	8	26733	0	0	0	80000	10	26738	26737	26715	26737	26737
80024	26715	200	1	1	1	2	0	0	0	0	66	1	0	3	26699	3	7	7	19	25	80010	10	80000	10	80000	50	1173975	1	49	23656	26737	26736	16681	3	16823	80010	20	80000	20	160000	26736	85	1	1	80021	10	9	10	80000	10	80000	0	10	80019	20	43	0	80059	1	0	1	64	80000	6	0	59	43	19	0	5020	0	17	16	0	16	17	26733	13	13	5	80000	10	26737	26738	26738	26738	26737
80024	26714	201	0	1	1	0	0	0	0	0	67	1	0	2	26700	3	7	7	20	25	80010	10	80000	10	80000	50	1167219	1	49	23657	26737	26736	16681	3	16695	80010	20	80000	20	160000	26753	85	1	1	80021	10	9	10	80000	10	80000	0	10	80019	19	43	0	80059	0	0	0	64	80039	6	0	59	43	19	2	5020	0	17	16	0	17	17	26734	13	13	5	80000	10	26737	26715	26737	26737	26738
80024	26737	200	0	1	1	0	1	0	0	0	67	1	0	0	26721	3	7	7	20	25	80010	10	80000	10	80000	50	1167106	0	49	23635	26737	26736	16681	3	16803	80010	20	80000	20	160000	26736	85	1	1	80021	10	9	10	80000	10	80000	0	10	80019	19	43	0	80059	1	0	2	60	80040	0	0	58	44	19	2	5020	0	17	16	0	15	17	26734	13	13	0	80000	10	26715	26737	26737	26737	26737
80024	26736	200	0	1	0	0	0	0	0	0	67	1	0	3	26721	3	0	0	0	25	80010	10	80000	10	80000	50	1167219	1	49	23656	26736	26715	16682	3	16783	80010	20	80000	20	160000	26736	85	1	1	80021	10	9	10	80000	10	80000	0	10	80020	19	45	0	80058	1	1	1	21	80041	6	1	59	43	19	0	5020	0	16	16	0	17	17	26733	13	13	0	80000	10	26737	26716	26737	26737	26738
80024	26737	200	0	1	1	1	0	0	0	0	67	1	0	3	26721	3	7	7	0	25	80010	10	80000	10	80000	50	1167834	1	49	23656	26736	26736	16660	3	16720	80010	20	80000	20	160000	26736	85	1	1	80021	10	9	10	80000	10	80000	1	10	80019	19	43	0	80019	0	1	0	61	80000	6	1	59	43	19	1	5020	0	9	16	0	16	9	26733	13	13	5	80000	10	26737	26738	26737	26737	26737
80024	26736	200	0	1	1	1	0	0	0	0	66	1	0	3	26721	3	7	7	20	25	80010	10	80000	10	80000	50	1167106	1	49	23656	26736	26736	16660	3	16756	80010	20	80000	20	160000	26717	85	1	1	80021	10	9	10	80000	10	80000	0	10	80021	21	0	0	80019	1	0	1	61	80040	6	1	59	45	19	1	5020	0	17	16	0	18	16	26733	13	13	5	80000	10	26716	26737	26737	26737	26737
80024	26736	200	0	1	1	0	0	0	0	0	21	1	0	3	26721	3	7	7	22	25	80010	10	80000	10	80000	50	1167219	1	49	23656	26736	26736	16682	3	16815	80010	20	80000	20	160000	26736	85	1	1	80021	10	9	10	80000	10	80000	0	10	80019	20	43	0	80058	1	0	2	60	80040	6	1	59	0	19	2	5020	0	15	16	0	17	17	26712	13	13	5	80000	10	26737	26737	26737	26737	26738
80024	26737	201	0	1	1	1	1	0	0	0	22	1	0	2	26700	3	7	7	20	25	80010	10	80000	10	80000	50	1167219	1	49	23657	26736	26736	16682	3	16795	80010	20	80000	20	160000	26736	64	1	1	80021	10	9	10	80000	10	80000	0	10	80019	19	0	0	80059	1	0	1	60	80000	6	1	59	43	19	1	5020	0	17	16	0	17	17	26733	13	13	5	80000	10	26737	26737	26737	26716	26738
80024	26737	200	0	1	0	0	0	0	0	0	21	1	0	2	26722	2	9	7	20	25	80010	10	80000	10	80000	50	1167791	1	49	23656	26737	26737	16681	3	16784	80010	20	80000	20	160000	26736	85	1	1	80021	10	9	10	80000	10	80000	0	10	80019	20	43	0	80059	1	0	0	61	80040	6	1	58	43	19	1	5020	0	14	16	0	17	14	26711	13	0	5	80000	10	26737	26737	26716	26737	26738

LDRSB (register, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations