Firestorm: LDRSH (register, 32-bit) measurements

Code:

  ldrsh w0, [x6, x7]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	1e	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	394	3	1	0	45	1	1	379	2	12	12	16	25	1000	1000	1000	15018	0	394	394	216	3	252	1000	1000	2000	394	77	1	1	1001	1000	1000	0	1000	43	1039	0	39	1000	6	1	39	43	73	2	16	2	2	391	10	10	4	1000	395	395	395	395	395
1004	394	3	0	0	45	1	1	379	2	12	12	16	25	1000	1000	1000	15018	0	394	394	216	3	252	1000	1000	2000	394	77	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	39	43	73	2	16	2	2	371	10	10	4	1000	395	395	395	395	395
1004	394	3	0	1	45	1	1	379	2	12	12	16	25	1000	1000	1000	14989	0	394	394	221	3	252	1000	1000	2000	394	56	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	39	43	73	2	16	2	2	391	10	10	4	1000	395	398	395	395	395
1004	394	3	0	0	45	0	1	379	2	12	12	16	25	1000	1000	1000	14989	0	394	394	217	3	252	1000	1000	2000	374	77	1	1	1001	1000	1000	0	1000	0	1039	0	39	1039	6	1	39	43	73	2	16	2	2	391	10	10	4	1000	395	395	395	395	395
1004	394	3	0	0	45	0	1	379	2	12	12	0	25	1000	1000	1000	15037	0	394	394	197	3	252	1000	1000	2000	394	77	1	1	1001	1000	1000	0	1000	43	1039	0	0	1039	6	0	0	43	73	2	16	2	2	391	0	0	4	1000	395	395	395	395	395
1004	394	3	1	0	45	1	1	379	2	12	12	16	25	1000	1000	1000	15037	0	394	394	217	3	252	1000	1000	2000	394	56	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	0	1	39	43	73	2	16	2	2	391	10	10	4	1000	395	395	395	395	395
1004	394	3	0	0	45	1	0	379	2	12	12	19	25	1000	1000	1000	15018	1	394	394	217	3	252	1000	1000	2000	394	77	1	1	1001	1000	1000	0	1000	43	1039	0	39	1000	6	1	39	43	73	2	16	2	2	391	10	10	4	1000	395	395	395	395	395
1004	394	2	0	0	45	1	1	379	2	12	12	16	25	1000	1000	1000	14989	1	394	394	217	3	252	1000	1000	2000	394	77	1	1	1001	1000	1000	0	1000	43	1039	0	0	1039	6	1	39	0	73	2	16	2	2	391	10	10	4	1000	395	395	395	395	395
1004	394	3	0	0	45	1	1	379	2	12	0	16	25	1000	1000	1000	15018	1	394	394	217	3	252	1000	1000	2000	394	77	1	1	1001	1000	1000	0	1000	43	1039	0	0	1039	6	1	39	0	73	2	16	2	2	391	10	10	4	1000	395	395	395	395	395
1004	394	3	0	1	45	1	1	379	2	12	12	16	25	1000	1000	1000	15037	1	394	394	197	3	252	1000	1000	2000	394	77	1	1	1001	1000	1000	0	1000	43	1039	1	40	1039	6	1	39	43	73	2	16	2	2	391	10	10	4	1000	395	395	395	395	395

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh w0, [x6, x7]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70051	525	1	0	0	0	1	0	70039	69764	59710	25	40104	30103	10002	30100	10051	621189	3341470	49	66974	70051	70054	64650	3	64957	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	0	1	0	2610	1	71	1	1	69817	30003	10	10	13	10000	30100	70036	70052	70055	70055	70055
40204	70051	524	0	0	0	6	1	0	70036	69785	59710	25	40100	30103	10000	30100	10000	616175	3342254	49	66974	70054	70051	64647	3	64938	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	0	0	0	2610	1	71	1	1	69798	30003	10	10	13	10000	30100	70055	70036	70055	70055	70053
40204	70051	525	0	0	0	58	0	0	70036	69782	59710	25	40104	30103	10001	30100	10000	616014	3341470	49	66971	70054	70054	64631	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	0	0	1	0	2610	1	71	1	1	69817	30000	13	0	13	10000	30100	70052	70055	70052	70036	70036
40204	70035	524	0	0	0	1	1	0	70039	69764	59710	25	40104	30103	10000	30100	10000	616014	3342254	49	66955	70051	70051	64647	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	0	1	0	2610	1	71	1	1	69817	30003	13	10	0	10000	30100	70055	70055	70052	70052	70036
40204	70054	525	0	0	0	1	0	0	70039	69785	59713	25	40104	30117	10001	30100	10102	618583	3342254	49	66974	70035	70054	64631	3	64954	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	0	1	0	2610	1	71	1	1	69814	30003	10	10	10	10000	30100	70036	70052	70055	70055	70052
40204	70051	525	0	0	0	6	1	0	70020	69785	59740	25	40104	30100	10001	30100	10000	616014	3342254	49	66955	70051	70035	64647	3	64938	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	0	10000	1	0	1	0	2610	1	71	1	1	69814	30003	13	10	10	10000	30100	70058	70057	70053	70055	70055
40204	70051	525	0	0	0	0	1	0	70036	69764	59710	25	40104	30103	10001	30100	10000	616014	3341470	49	66971	70054	70054	64647	3	64938	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	0	10000	1	0	1	0	2610	1	71	1	1	69814	30003	10	10	10	10000	30100	70052	70055	70052	70052	70036
40204	70035	525	0	0	0	1	0	0	70036	69782	59710	25	40104	30103	10001	30100	10000	616041	3342254	98	66988	70054	70051	64631	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	10000	0	0	0	10000	1	0	0	0	2610	1	71	1	1	69814	30003	13	0	13	10000	30100	70055	70055	70055	70052	70036
40204	70035	524	0	0	0	0	1	0	70020	69785	59695	25	40104	30103	10000	30100	10000	616041	3342254	49	66955	70051	70051	64647	3	64938	40100	30200	10000	60200	20000	70054	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	0	1	0	2610	1	71	1	1	69818	30003	10	0	0	10000	30100	70052	70036	70052	70055	70036
40204	70051	524	0	0	0	10	1	0	70036	69785	59695	25	40100	30100	10000	30100	10000	616175	3342398	49	66955	70035	70035	64631	3	64957	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	0	1	0	2610	1	71	1	1	69816	30003	13	10	10	10000	30100	70036	70036	70052	70055	70036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70047	525	1	0	0	0	0	0	1	0	0	0	70035	69760	59706	25	40010	30013	10001	30010	10000	616982	3342062	0	49	66967	70050	70050	64668	3	64975	40010	30020	10000	60020	20000	70050	35	2	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	0	10000	1	1	0	0	2520	1	71	1	2	69813	30000	9	6	9	10000	30010	70051	70051	70036	70051	70036
40024	70035	524	0	0	0	1	0	0	1	0	0	0	70035	69760	59695	25	40014	30010	10001	30010	10000	616982	3342206	0	49	66955	70050	70050	64653	3	64975	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	2520	1	71	1	1	69798	30003	9	0	9	10000	30010	70051	70051	70051	70036	70051
40024	70035	525	0	0	0	0	0	0	6	0	0	0	70035	69760	59706	25	40014	30013	10001	30010	10000	616982	3342206	0	49	66970	70050	70050	64653	3	64975	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	2520	1	71	1	1	69813	30003	9	6	9	10000	30010	70036	70036	70051	70051	70041
40024	70047	525	0	0	0	0	0	0	6	0	0	0	70035	69760	59712	25	40014	30010	10001	30010	10000	617068	3342206	0	49	66955	70050	70050	64668	3	64960	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	0	10000	1	1	0	0	2520	1	71	1	2	69813	30003	9	6	9	10000	30010	70048	70051	70036	70051	70051
40024	70050	525	0	0	0	0	0	0	1	0	1	0	70032	69728	59706	25	40026	30013	10001	30010	10000	619359	3345794	0	49	66973	70050	70047	64653	3	64960	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	1	0	10000	1	0	0	0	2520	1	71	1	2	69810	30003	6	6	9	10000	30010	70051	70051	70048	70036	70051
40024	70035	525	0	0	0	0	0	0	0	0	0	0	70035	69760	59709	25	40014	30013	10001	30010	10000	617068	3342206	0	49	66970	70050	70035	64665	3	64975	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	2520	2	71	2	1	69813	30003	9	9	9	10000	30010	70093	70050	70040	70053	70048
40024	70050	524	0	0	0	0	0	0	0	0	0	0	70020	69743	59695	25	40014	30013	10000	30010	10000	616982	3341470	0	49	66970	70050	70035	64668	3	64960	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	10000	0	0	10000	0	0	0	0	2520	2	71	1	1	69813	30003	6	6	9	10000	30010	70051	70051	70051	70051	70051
40024	70035	524	0	0	0	0	0	0	1	0	0	0	70035	69743	59709	25	40014	30010	10001	30010	10000	616982	3342206	0	49	66970	70050	70035	64668	3	64960	40010	30020	10000	60020	20000	70047	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	0	0	0	2520	1	71	1	1	69813	30003	9	6	9	10000	30010	70051	70036	70048	70048	70051
40024	70050	524	0	0	0	0	0	0	1	0	0	0	70020	69748	59709	25	40014	30013	10001	30010	10000	616982	3342206	0	49	66967	70050	70050	64668	3	64960	40218	30020	10000	60020	20000	70050	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	0	0	0	2520	1	71	1	1	69813	30000	9	6	9	10000	30010	70041	70036	70053	70036	70036
40024	70050	524	0	0	0	0	0	0	1	0	1	0	70032	69760	59709	25	40014	30013	10001	30010	10000	617068	3342062	1	49	66970	70050	70035	64668	3	64975	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	1	10000	0	3	10000	1	1	0	0	2520	1	71	1	1	69813	30003	9	0	9	10000	30010	70048	70051	70036	70036	70051

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh w0, [x6, x7]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	1e	22	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70047	525	0	0	1	1	70035	69781	59709	25	40104	30103	10002	30100	10000	616175	3342062	1	49	66970	70035	70050	64646	3	64953	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	0	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	1	0	0	0	2610	2	71	2	2	69798	30003	6	6	6	10000	30100	70051	70048	70051	70048	70051
40204	70050	524	0	0	1	1	70032	69735	59695	25	40104	30103	10000	30100	10000	616175	3341470	1	49	66967	70047	70047	64646	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	0	100	10000	30100	10000	0	100	10000	1	10000	0	0	3	10000	1	1	0	0	0	2610	2	71	2	2	69810	30003	6	0	9	10000	30100	70048	70048	70048	70051	70036
40204	70053	524	0	0	1	0	70035	69781	59709	25	40100	30103	10001	30100	10000	616005	3342206	1	49	63942	70050	70047	64643	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	0	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	1	0	0	0	2610	2	71	2	2	69810	30003	6	6	0	10000	30100	70052	70048	70051	70066	70059
40204	70050	524	0	0	1	1	70032	69781	59706	25	40104	30103	10001	30100	10000	616015	3342062	1	49	66970	70047	70047	64646	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	0	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	0	0	0	0	2610	2	71	2	2	69810	30003	0	9	6	10000	30100	70051	70051	70048	70036	70051
40204	70047	524	0	0	1	0	70032	69735	59706	25	40104	30103	10001	30100	10000	616005	3342062	1	49	66967	70035	70050	64631	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	0	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	1	0	0	0	2610	2	71	2	2	69798	30003	6	6	9	10000	30100	70051	70051	70048	70048	70051
40204	70047	525	0	0	1	1	70035	69735	59706	25	40104	30103	10001	30100	10000	616005	3341470	1	49	66970	70050	70047	64631	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	0	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	0	1	0	0	0	2610	2	71	2	2	69811	30003	6	6	6	10000	30100	70051	70051	70048	70048	70048
40204	70050	524	0	0	1	1	70035	69735	59709	25	40104	30103	10001	30100	10000	616175	3342206	1	49	66967	70035	70047	64646	3	64950	40100	30200	10000	60200	20000	70151	35	1	1	40201	100	99	0	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	1	0	0	0	2610	2	71	2	2	69810	30003	6	6	6	10000	30100	70051	70051	70048	70048	70048
40204	70035	524	0	0	1	0	70032	69735	59709	25	40104	30103	10001	30100	10000	616033	3342206	1	49	66967	70035	70035	64643	3	64953	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	0	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	1	0	0	0	2610	2	71	2	2	69800	30003	6	6	6	10000	30100	70051	70048	70048	70048	70036
40204	70035	524	0	0	1	0	70032	69737	59706	25	40104	30103	10001	30100	10000	616015	3342206	1	49	66967	70049	70047	64713	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	0	100	10000	30100	10000	1	100	10000	1	10000	0	0	0	10000	1	1	0	0	0	2610	2	71	2	2	69810	30003	9	9	0	10000	30100	70036	70048	70051	70051	70051
40204	70050	524	1	1	55	1	70032	69735	59706	25	40100	30100	10001	30100	10000	616015	3342483	1	49	66967	70047	70047	64643	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	0	100	10000	30100	10000	0	100	10000	1	10000	0	0	0	10000	1	1	0	0	0	2610	2	71	2	2	69810	30003	0	0	9	10000	30100	70048	70048	70036	70048	70036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	23	24	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70051	524	1	0	1	0	1	1	0	0	118	1	0	0	3	70036	69781	59710	25	40014	30013	10002	30010	10000	616991	3342254	0	49	67081	70057	70056	64669	3	65028	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	10000	1	0	0	2526	16	71	19	15	69798	30003	10	10	13	10000	30010	70052	70036	70036	70052	70036
40024	70051	525	1	0	1	0	0	0	0	0	0	1	0	0	3	70036	69743	59713	25	40014	30013	10001	30010	10000	616991	3341470	0	49	66977	70094	70074	64671	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	10000	0	1	0	2526	15	71	17	21	69817	30003	10	10	10	10000	30010	70055	70052	70036	70052	70052
40024	70051	525	1	0	1	0	0	0	0	0	1	0	0	0	3	70036	69775	59695	25	40010	30010	10001	30010	10000	616991	3342254	0	49	66971	70080	70077	64671	3	64960	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	2526	16	71	18	17	69814	30003	10	10	10	10000	30010	70052	70052	70052	70036	70052
40024	70056	526	1	0	1	0	0	0	0	0	1	0	0	0	3	70036	69775	59713	25	40014	30013	10001	30010	10000	616991	3342254	0	49	66971	70086	70092	64669	3	64982	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	2526	16	71	19	18	69798	30003	0	10	10	10000	30010	70052	70052	70052	70036	70036
40024	70037	525	1	0	1	0	0	0	0	0	0	0	0	0	3	70036	69743	59695	25	40014	30010	10000	30010	10000	617018	3342254	0	49	67064	70052	70051	64672	3	64979	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	3	10000	0	0	0	2526	16	71	16	13	69814	30014	10	10	10	10000	30010	70052	70036	70052	70052	70036
40024	70051	524	1	0	1	0	0	0	0	1	37	1	0	0	3	70036	69775	59695	25	40014	30010	10001	30010	10000	617068	3342254	0	49	67066	70053	70053	64744	3	64960	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	2	1	10000	1	0	10000	1	1	0	2526	15	71	19	15	69818	30003	10	13	0	10000	30010	70036	70052	70052	70052	70052
40024	70037	525	1	0	1	0	0	0	0	0	0	1	0	0	3	70036	69743	59713	25	40014	30013	10000	30010	10000	617068	3342254	0	49	66971	70102	70096	64678	3	64976	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	3	10000	1	1	0	2526	16	87	19	19	69815	30010	0	10	0	10000	30010	70240	70036	70036	70055	70052
40024	70054	525	1	0	1	0	0	0	0	0	1	0	0	0	3	70126	69775	59695	25	40014	30013	10001	30010	10000	617068	3342254	0	49	66971	70106	70094	64673	3	64978	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10005	0	1	10000	0	0	10000	1	1	0	2526	16	71	16	17	69814	30000	0	10	10	10000	30010	70052	70036	70053	70141	70039
40024	70035	524	1	0	1	0	0	0	0	0	1	0	0	0	3	70036	69776	59713	25	40014	30013	10001	30010	10000	619285	3342254	0	49	67071	70335	70051	64716	3	64960	40010	30020	10165	60020	20220	70436	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	1	0	2526	17	71	20	18	69814	30003	10	10	10	10000	30010	70052	70052	70036	70036	70036
40024	70051	524	1	0	1	0	1	1	0	0	13	1	0	0	3	70036	69743	59695	25	40014	30013	10001	30010	10000	616991	3342398	0	49	66971	70094	70055	64669	3	64978	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	10000	1	1	0	2526	17	71	14	14	69814	30003	10	10	10	10000	30010	70052	70052	70052	70055	70052

Test 4: throughput

Count: 8

Code:

  ldrsh w0, [x6, x7]
  ldrsh w0, [x6, x7]
  ldrsh w0, [x6, x7]
  ldrsh w0, [x6, x7]
  ldrsh w0, [x6, x7]
  ldrsh w0, [x6, x7]
  ldrsh w0, [x6, x7]
  ldrsh w0, [x6, x7]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26715	201	1	0	1	0	0	0	0	21	0	1	0	3	26717	2	18	0	16	25	80100	100	80000	100	80016	500	1167095	0	49	23652	26733	26714	16659	6	16684	80115	200	80024	200	160048	26889	81	1	1	80201	100	99	100	80000	100	80000	1	100	80019	19	42	0	80057	0	0	0	21	80038	6	1	57	42	19	1	1	1	1	5118	2	16	26711	9	9	0	80000	100	26733	26733	26734	26733	26734
80204	26714	201	1	0	1	1	0	0	0	21	0	0	0	2	26717	2	18	18	16	25	80100	100	80000	100	80015	500	1167653	0	49	23652	26732	26732	16642	6	16666	80115	200	80024	200	160048	26895	81	1	1	80201	100	99	100	80000	100	80000	0	100	80019	19	0	0	80019	1	0	1	21	80000	6	0	19	0	19	1	1	1	1	5118	0	16	26736	9	9	2	80000	100	26805	26715	26733	26734	26733
80204	26732	200	1	1	1	0	1	0	0	21	0	0	0	2	26724	0	18	18	15	25	80100	100	80000	100	80016	500	1169757	0	49	23653	26732	26732	16672	6	16684	80116	200	80024	200	160048	26907	64	1	1	80201	100	99	100	80000	100	80000	0	100	80019	20	42	0	80187	1	0	1	59	80038	6	1	19	0	19	0	1	1	1	5118	0	16	26729	9	9	2	80000	100	26715	26734	26733	26733	26715
80204	26714	200	1	0	1	0	0	0	0	21	0	1	0	3	26717	2	18	18	16	25	80100	100	80000	100	80015	500	1167763	0	49	23653	26732	26732	16660	6	16666	80115	200	80024	200	160048	26732	81	1	1	80201	100	99	100	80000	100	80000	0	100	80020	28	0	0	80057	0	0	0	59	80038	0	0	57	42	18	0	1	1	1	5118	0	16	26711	0	9	2	80000	100	26733	26734	26733	26715	26734
80204	26714	200	1	0	0	0	0	0	0	65	0	0	0	1	26717	3	18	18	16	25	80100	100	80000	100	80016	500	1167107	0	49	23652	26715	26733	16659	6	16685	80114	200	80024	200	160048	26733	82	1	1	80201	100	99	100	80000	100	80000	0	100	80019	21	42	0	80019	0	0	0	59	80038	6	1	19	42	19	0	1	1	1	5118	0	16	26730	0	0	2	80000	100	26734	26733	26733	26733	26733
80204	26714	200	1	0	0	0	0	0	0	21	0	1	0	0	26717	0	0	18	16	25	80100	100	80000	100	80015	500	1168061	0	49	23652	26732	26733	16660	6	16684	80116	200	80024	200	160048	26733	82	1	1	80201	100	99	100	80000	100	80000	0	100	80021	19	42	0	80019	1	1	0	59	80038	6	1	57	42	19	2	1	1	1	5118	0	16	26711	0	0	2	80000	100	26733	26733	26733	26733	26715
80204	26714	200	1	1	0	0	0	0	0	65	0	1	0	2	26699	0	18	18	16	25	80100	100	80000	100	80016	500	1166590	0	49	23634	26733	26732	16660	6	16684	80115	200	80024	200	160048	26732	81	1	1	80201	100	99	100	80000	100	80000	0	100	80020	20	42	0	80057	0	0	1	59	80000	6	1	19	41	19	0	1	1	1	5118	0	16	26737	9	9	0	80000	100	26733	26715	26733	26733	26715
80204	26732	200	1	0	0	0	0	0	0	65	0	0	0	2	26699	0	18	18	15	25	80100	100	80000	100	80015	500	1167763	0	49	23653	26732	26733	16660	6	16684	80116	200	80024	200	160048	26732	81	1	1	80201	100	99	100	80000	100	80000	0	100	80020	20	0	0	80057	0	0	0	60	80038	6	0	57	0	19	1	1	1	1	5118	0	16	26729	9	9	0	80000	100	26733	26716	26733	26715	26734
80204	26714	200	1	0	1	0	0	0	0	21	0	1	0	3	26717	2	0	18	0	25	80100	100	80000	100	80015	500	1166836	0	49	23653	26732	26714	16660	6	16684	80115	200	80024	200	160048	26732	81	1	1	80201	100	99	100	80000	100	80000	0	100	80021	19	42	0	80019	1	0	2	59	80000	6	1	57	42	19	0	1	1	1	5118	0	16	26711	0	9	2	80000	100	26733	26733	26733	26715	26733
80204	26714	200	1	1	0	0	0	0	0	21	0	0	0	3	26717	2	0	18	0	25	80100	100	80000	100	80016	500	1167733	0	49	23634	26733	26714	16642	6	16684	80113	200	80024	200	160048	26794	81	1	1	80201	100	99	100	80000	100	80000	0	100	80020	20	42	0	80057	0	0	2	21	80037	6	1	57	42	19	2	1	1	1	5118	0	16	26711	9	0	2	80000	100	26733	26733	26734	26733	26734

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3341

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	0f	18	19	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cd	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26722	200	0	0	0	0	0	75	0	0	2	26707	0	18	18	16	25	80010	10	80000	10	80000	50	1172240	1	49	23697	26728	26758	16682	3	16688	80010	20	80000	20	160000	26722	71	1	1	80021	10	9	10	80000	10	80000	1	10	80000	0	39	80035	0	0	0	39	80035	6	1	35	0	0	5020	0	16	16	11	10	26725	0	6	4	80000	10	26729	26729	26709	26729	26728
80024	26722	200	0	0	0	0	0	45	1	0	2	26693	2	0	12	16	25	80010	10	80000	10	80000	50	1168843	1	49	23633	26736	26734	16672	3	16688	80010	20	80000	20	160000	26727	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	43	80039	0	0	0	39	80039	6	1	0	43	0	5020	0	12	16	12	13	26719	6	0	4	80000	10	26723	26728	26709	26729	26709
80024	26708	201	0	0	0	0	0	0	0	0	2	26712	2	12	12	16	25	80010	10	80000	10	80000	50	1166750	1	49	23770	26735	26731	16681	3	16702	80010	20	80000	20	160000	26708	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	80039	0	0	0	0	80039	0	0	35	43	0	5020	0	12	16	12	12	26725	10	6	4	80000	10	26709	26728	26728	26709	26709
80025	26708	201	1	0	0	0	0	0	0	0	2	26707	0	0	12	0	25	80010	10	80000	10	80000	50	1166886	1	49	23767	26716	26716	16672	3	16708	80010	20	80000	20	160000	26727	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	39	80039	0	0	0	39	80000	0	0	39	43	0	5020	0	10	16	11	11	26705	10	0	4	80000	10	26728	26709	26728	26728	26728
80024	26708	200	0	0	0	0	0	45	0	0	2	26693	0	12	12	16	25	80010	10	80000	10	80000	50	1166750	1	49	23743	26733	26735	16672	3	16688	80010	20	80000	20	160000	26728	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	80039	0	0	0	35	80035	0	1	39	43	0	5020	0	12	16	13	10	26724	6	0	0	80000	10	26728	26728	26709	26729	26729
80024	26728	200	0	0	0	0	0	45	0	0	2	26693	0	12	12	16	25	80010	10	80000	10	80000	50	1166750	1	49	23753	26734	26738	16710	3	16707	80010	20	80000	20	160000	26727	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	80039	0	0	0	39	80039	6	1	35	0	0	5020	0	13	16	12	13	26705	10	10	4	80000	10	26728	26729	26729	26729	26728
80024	26708	200	0	0	1	0	3	54	1	0	0	26712	2	0	12	16	25	80010	10	80000	10	80000	50	1166750	1	49	23648	26728	26862	16679	3	16708	80010	20	80000	20	160000	26728	77	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	39	80039	0	0	0	35	80039	6	0	36	0	0	5020	0	10	16	12	12	26705	10	0	4	80000	10	26730	26728	26729	26723	26709
80024	26708	200	0	0	0	0	0	0	1	0	1	26713	2	12	0	16	25	80010	10	80000	10	80000	50	1166896	1	49	23753	26734	26736	16693	3	16702	80010	20	80000	20	160000	26708	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	39	80039	0	1	0	39	80000	6	0	39	43	0	5020	0	12	16	13	10	26705	10	10	0	80000	10	26709	26709	26709	26709	26729
80024	26728	200	0	0	0	0	0	0	0	0	2	26712	2	0	0	16	25	80010	10	80000	10	80000	50	1167605	1	49	23748	26741	26736	16662	3	16707	80010	20	80000	20	160000	26708	71	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	43	80000	0	0	0	35	80039	6	1	0	0	0	5020	0	13	16	10	13	26705	10	6	0	80000	10	26729	26709	26729	26723	26723
80024	26722	200	0	0	0	0	0	45	1	0	2	26713	0	12	12	16	25	80010	10	80000	10	80000	50	1166750	1	49	23648	26708	26897	16663	3	16711	80010	20	80000	20	160000	26708	71	1	1	80021	10	9	10	80000	10	80000	1	10	80000	0	39	80035	0	0	0	0	80039	0	1	35	43	0	5020	0	12	16	12	13	26725	10	10	0	80000	10	26733	26709	26731	26729	26723

LDRSH (register, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations