Firestorm: STRB (register, uxtw) measurements

Code:

  strb w0, [x6, w7, uxtw]

Initialization

  mov x0, 0
  mov x7, 8

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	22	3a	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	543	4	0	0	0	0	3	0	0	527	16	16	1	25	1000	1000	1000	22448	0	542	554	355	3	400	1000	1000	3000	543	542	1	1	1001	1000	1000	1000	0	42	0	0	1002	0	0	2	1002	2	42	0	0	73	2	16	1	1	539	1000	543	544	544	544	544
1004	543	4	0	0	0	0	3	0	0	527	16	16	1	25	1000	1000	1000	22472	0	542	542	356	3	400	1000	1000	3000	543	543	1	1	1001	1000	1000	1000	0	42	0	0	1002	0	0	2	1002	2	42	0	0	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	0	0	0	0	3	0	0	527	16	16	1	25	1000	1000	1000	22472	1	542	542	355	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	0	42	0	0	1002	0	0	2	1002	2	42	0	0	73	1	16	1	1	539	1000	543	543	543	543	544
1004	543	4	0	0	0	0	3	0	0	539	16	16	0	25	1000	1000	1000	22448	1	542	542	355	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	0	42	0	0	1002	0	0	2	1002	2	42	0	0	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	0	0	0	0	3	0	0	527	16	16	0	25	1000	1000	1000	22448	1	542	542	355	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	0	42	0	0	1002	0	0	5	1002	2	42	0	0	73	1	16	1	1	539	1000	543	544	544	544	544
1004	542	4	0	0	0	0	3	0	0	527	16	16	0	25	1000	1000	1000	22448	0	543	542	355	3	401	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	0	42	1	0	1002	0	0	2	1002	2	42	0	0	73	1	16	1	1	539	1000	544	544	544	544	544
1004	543	4	0	0	0	0	3	0	0	527	16	16	1	25	1000	1000	1000	22472	0	542	542	356	3	401	1000	1000	3000	543	543	1	1	1001	1000	1000	1000	0	42	0	0	1002	0	0	5	1002	2	42	0	0	73	1	16	1	1	539	1000	544	544	544	544	544
1004	543	3	0	0	0	0	3	1	0	528	16	16	1	25	1000	1000	1000	22472	0	542	543	356	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	0	42	0	0	1002	0	0	2	1002	2	42	0	0	73	1	16	1	1	539	1000	543	543	543	543	543
1004	542	4	0	0	0	9	3	0	0	527	16	16	5	25	1000	1000	1000	22448	0	542	542	355	3	400	1000	1000	3000	543	543	1	1	1001	1000	1000	1000	0	42	0	0	1002	0	0	2	1002	16	42	0	0	73	1	16	1	1	539	1000	543	544	543	543	543
1004	542	4	0	0	0	0	3	0	0	527	16	16	1	25	1000	1000	1000	22472	0	542	543	356	3	400	1000	1000	3000	543	542	1	1	1001	1000	1000	1000	0	42	0	0	1002	0	0	2	1002	2	42	0	0	73	1	16	1	1	539	1000	543	543	543	543	543

Count: 8

Code:

  strb w0, [x6, w7, uxtw]
  strb w0, [x6, w7, uxtw]
  strb w0, [x6, w7, uxtw]
  strb w0, [x6, w7, uxtw]
  strb w0, [x6, w7, uxtw]
  strb w0, [x6, w7, uxtw]
  strb w0, [x6, w7, uxtw]
  strb w0, [x6, w7, uxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	19	1e	1f	22	23	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40058	300	0	0	0	3	0	0	40027	16	16	0	25	80100	100	80000	100	80007	500	1839378	0	49	36969	40042	40050	29968	7	30003	80107	200	80016	200	240048	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	0	80000	0	2	80002	0	34	1	1	1	5118	0	16	0	0	40039	0	80000	100	40041	40050	40043	40043	40041
80204	40050	300	0	0	0	0	0	0	40027	16	16	0	25	80100	100	80000	100	80007	500	1839378	0	49	36962	40040	40042	29961	7	29994	80107	200	80016	200	240048	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	34	0	80002	0	0	80002	0	34	1	1	1	5118	0	16	0	0	40039	0	80000	100	40043	40041	40043	40043	40051
80204	40042	300	0	0	0	0	1	0	40025	16	16	4	25	80100	100	80000	100	80007	500	1839455	0	49	36960	40051	40040	29969	7	30000	80107	200	80016	200	240048	40040	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	34	0	80002	0	2	80002	0	34	1	1	1	5118	0	16	0	0	40037	0	80000	100	40051	40041	40041	40043	40041
80204	40040	299	0	0	6	6	1	0	40027	16	16	0	25	80100	100	80000	100	80007	500	1839378	0	49	36960	40042	40040	29961	7	29994	80107	200	80016	200	240048	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	34	0	80000	0	0	80002	2	34	1	1	1	5118	0	16	0	0	40039	0	80000	100	40043	40050	40043	40043	40043
80204	40050	300	0	0	0	0	0	0	40025	0	16	0	25	80100	100	80000	100	80007	500	1839455	0	49	36960	40040	40051	29959	7	30001	80106	200	80016	200	240048	40042	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	34	0	80002	0	0	80002	0	34	1	1	1	5118	0	16	0	0	40039	0	80000	100	40052	40043	40052	40043	40041
80204	40042	300	0	0	0	3	0	0	40027	16	16	0	25	80100	100	80000	100	80007	500	1839455	0	49	36962	40040	40042	29961	7	29994	80107	200	80016	200	240048	40040	31993	1	1	80201	100	99	100	80000	100	80000	100	80000	0	34	0	80002	0	8	80002	2	34	1	1	1	5118	0	16	0	0	40039	0	80000	100	40041	40043	40050	40043	40041
80204	40040	300	0	0	0	0	0	0	40566	16	0	402	85	80220	100	80180	100	80006	500	1839455	1	49	36962	40042	40040	29961	20	30363	80107	200	80016	200	240048	40040	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	2	34	88	80120	0	1090	80122	2	34	1	1	1	5118	0	16	0	0	40945	0	80000	100	40740	41430	41421	41292	40735
80204	41427	310	1	0	0	6	0	0	40027	0	16	0	25	80100	100	80000	100	80013	500	1839381	0	49	36962	40042	40050	29950	10	29980	80112	200	80022	200	240066	40040	39481	1	1	80201	100	99	100	80000	100	80000	100	80000	0	34	0	80002	0	2	80002	2	34	2	2	2	5128	1	23	1	1	40039	0	80000	100	40043	40043	40052	40043	40043
80204	40042	300	0	0	0	3	0	0	40027	0	0	0	25	80100	100	80000	100	80012	500	1839316	0	49	36960	40042	40040	29952	10	29980	80113	200	80022	200	240066	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	34	0	80002	0	2	80000	2	34	2	2	2	5128	1	23	1	1	40039	0	80000	100	40051	40043	40051	40043	40041
80204	40040	300	0	0	0	0	0	1	40027	0	0	0	25	80100	100	80000	100	80013	500	1839381	0	49	36962	40049	40042	29952	10	29980	80113	200	80022	200	240066	40040	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	0	0	0	80002	0	8	80000	2	0	2	2	2	5128	1	23	1	1	40037	0	80000	100	40041	40043	40043	40043	40043

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	c2	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40043	300	0	0	0	0	0	0	0	0	0	0	0	40027	16	0	1	25	80010	10	80000	10	80000	50	1839352	1	49	36962	40040	40042	29975	3	30020	80010	20	80000	20	240000	40042	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	42	0	0	80000	0	0	9	80002	2	0	0	0	5020	0	25	16	15	15	40039	0	80000	10	40041	40041	40043	40041	40041
80024	40042	300	0	0	0	0	0	0	0	3	1	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839448	1	49	36960	40042	40042	29978	3	30020	80010	20	80000	20	240000	40042	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	0	0	80002	1	0	0	80002	2	0	0	0	5020	0	19	16	14	13	40040	0	80000	10	40055	40041	40043	40043	40043
80024	40040	300	0	0	0	0	0	0	0	0	0	0	0	40025	16	0	0	25	80010	10	80000	10	80000	50	1839448	1	49	36962	40042	40042	29975	3	30022	80010	20	80000	20	240000	40042	40054	1	1	80021	10	9	10	80000	10	80000	10	80000	0	42	0	0	80002	0	0	0	80000	2	0	0	0	5020	0	15	16	9	19	40037	0	80000	10	40044	40043	40041	40044	40043
80024	40043	300	0	0	0	0	0	0	0	3	0	0	0	40027	0	16	0	25	80010	10	80000	10	80000	50	1839352	1	49	36960	40042	40042	29977	3	30022	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	0	0	80002	0	0	2	80002	2	0	0	0	5020	0	19	16	15	9	40039	0	80000	10	40041	40043	40041	40041	40043
80024	40040	300	0	0	0	0	0	0	9	3	1	0	0	40027	16	16	0	25	80010	10	80000	10	80000	50	1839448	0	49	36963	40043	40043	29977	3	30023	80010	20	80000	20	240000	40040	40043	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	0	0	80000	0	0	2	80000	0	0	0	0	5020	0	15	16	14	8	40039	0	80000	10	40043	40043	40041	40043	40043
80024	40054	300	0	0	0	0	0	0	0	3	0	0	0	40027	16	0	1	25	80010	10	80000	10	80000	50	1839472	0	49	36962	40043	40042	29975	3	30022	80010	20	80000	20	240000	40042	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	0	0	80000	0	0	2	80000	2	42	0	0	5020	0	15	16	15	13	40037	0	80000	10	40041	40041	40043	40041	40041
80024	40042	300	0	0	0	0	0	0	0	3	1	0	0	40025	16	0	0	25	80010	10	80000	10	80000	50	1839448	1	49	36974	40042	40042	29977	3	30022	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	42	1	0	80002	0	0	2	80002	0	0	0	0	5020	0	9	16	7	15	40037	0	80000	10	40043	40041	40043	40043	40041
80024	40042	300	0	0	0	0	0	0	0	3	0	0	0	40025	16	0	0	25	80010	10	80000	10	80000	50	1839448	1	49	36962	40040	40042	29977	3	30034	80010	20	80000	20	240000	40040	40040	1	1	80021	10	9	10	80000	10	80000	10	80000	0	42	0	0	80000	0	0	2	80002	0	0	0	0	5020	0	15	16	9	19	40039	0	80000	10	40183	40182	40041	40043	40041
80024	40040	300	0	0	0	0	0	0	0	3	1	0	0	40027	16	16	1	25	80010	10	80000	10	80000	50	1839448	1	49	36962	40042	40042	29989	3	30022	80010	20	80000	20	240000	40040	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	42	0	0	80000	0	0	2	80000	2	42	0	0	5020	0	8	16	9	15	40039	0	80000	10	40043	40043	40041	40043	40044
80024	40043	300	0	0	0	0	0	0	0	0	1	0	0	40025	16	16	0	25	80070	10	80300	10	80216	50	1839448	1	49	36962	40042	40042	29978	3	30022	80010	20	80000	20	240000	40042	40042	1	1	80021	10	9	10	80000	10	80000	10	80000	0	0	0	0	80000	0	0	3	80002	0	42	0	0	5020	0	9	16	8	14	40039	0	80000	10	40043	40043	40041	40043	40041

STRB (register, uxtw)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations