Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
ubfiz x0, x0, #3, #7
mov x0, 1 mov x1, 2
(no loop instructions)
Retires: 1.000
Issues: 1.000
Integer unit issues: 1.000
Load/store unit issues: 0.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | 03 | 1e | 3f | 4d | 51 | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | 60 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst int alu (97) | l1d tlb access (a0) | l1d cache writeback (a8) | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 1004 | 1035 | 7 | 0 | 61 | 862 | 25 | 1000 | 1000 | 1000 | 16916 | 0 | 1035 | 1035 | 728 | 3 | 868 | 1000 | 1000 | 1000 | 1035 | 41 | 1 | 1 | 1001 | 1000 | 0 | 0 | 0 | 73 | 3 | 41 | 1 | 1 | 937 | 1000 | 1000 | 1036 | 1036 | 1036 | 1036 | 1036 |
| 1004 | 1035 | 7 | 0 | 61 | 862 | 25 | 1000 | 1000 | 1000 | 16916 | 0 | 1035 | 1035 | 728 | 3 | 868 | 1000 | 1000 | 1000 | 1035 | 41 | 1 | 1 | 1001 | 1000 | 0 | 0 | 0 | 73 | 1 | 41 | 1 | 1 | 937 | 1000 | 1000 | 1036 | 1036 | 1036 | 1036 | 1036 |
| 1004 | 1035 | 7 | 0 | 61 | 862 | 25 | 1000 | 1000 | 1000 | 16916 | 0 | 1035 | 1035 | 728 | 3 | 868 | 1000 | 1000 | 1000 | 1035 | 41 | 1 | 1 | 1001 | 1000 | 0 | 0 | 0 | 73 | 1 | 41 | 1 | 1 | 937 | 1000 | 1000 | 1036 | 1036 | 1036 | 1036 | 1036 |
| 1004 | 1035 | 7 | 0 | 61 | 862 | 25 | 1000 | 1000 | 1000 | 16916 | 0 | 1035 | 1035 | 728 | 3 | 868 | 1000 | 1000 | 1000 | 1035 | 41 | 1 | 1 | 1001 | 1000 | 0 | 0 | 0 | 73 | 1 | 41 | 1 | 1 | 937 | 1000 | 1000 | 1036 | 1036 | 1036 | 1036 | 1036 |
| 1004 | 1035 | 7 | 0 | 61 | 862 | 25 | 1000 | 1000 | 1000 | 16916 | 0 | 1035 | 1035 | 728 | 3 | 868 | 1000 | 1000 | 1000 | 1035 | 41 | 1 | 1 | 1001 | 1000 | 0 | 0 | 0 | 73 | 1 | 41 | 1 | 1 | 937 | 1000 | 1000 | 1036 | 1036 | 1036 | 1036 | 1036 |
| 1004 | 1035 | 7 | 0 | 61 | 862 | 25 | 1000 | 1000 | 1000 | 16916 | 0 | 1035 | 1035 | 728 | 3 | 868 | 1000 | 1000 | 1000 | 1035 | 41 | 1 | 1 | 1001 | 1000 | 0 | 0 | 0 | 73 | 1 | 41 | 1 | 1 | 937 | 1000 | 1000 | 1036 | 1036 | 1036 | 1036 | 1036 |
| 1004 | 1035 | 8 | 0 | 61 | 862 | 25 | 1000 | 1000 | 1000 | 16916 | 0 | 1035 | 1035 | 728 | 3 | 868 | 1000 | 1000 | 1000 | 1035 | 41 | 1 | 1 | 1001 | 1000 | 0 | 0 | 0 | 73 | 1 | 41 | 1 | 1 | 937 | 1000 | 1000 | 1036 | 1036 | 1036 | 1036 | 1036 |
| 1004 | 1035 | 8 | 0 | 61 | 862 | 25 | 1000 | 1000 | 1000 | 16916 | 0 | 1035 | 1035 | 728 | 3 | 868 | 1000 | 1000 | 1000 | 1035 | 41 | 1 | 1 | 1001 | 1000 | 0 | 0 | 0 | 73 | 1 | 41 | 1 | 1 | 937 | 1000 | 1000 | 1036 | 1036 | 1036 | 1036 | 1036 |
| 1004 | 1035 | 8 | 0 | 149 | 862 | 25 | 1000 | 1000 | 1000 | 16916 | 0 | 1035 | 1035 | 728 | 3 | 868 | 1000 | 1000 | 1000 | 1035 | 41 | 1 | 1 | 1001 | 1000 | 0 | 0 | 0 | 73 | 1 | 41 | 1 | 1 | 937 | 1000 | 1000 | 1036 | 1036 | 1036 | 1036 | 1036 |
| 1004 | 1035 | 8 | 0 | 89 | 862 | 25 | 1000 | 1000 | 1000 | 16916 | 0 | 1035 | 1035 | 728 | 3 | 868 | 1000 | 1000 | 1000 | 1035 | 41 | 1 | 1 | 1001 | 1000 | 0 | 0 | 6 | 73 | 1 | 41 | 1 | 1 | 937 | 1000 | 1000 | 1036 | 1036 | 1036 | 1036 | 1036 |
Code:
ubfiz x0, x0, #3, #7
mov x0, 1 mov x1, 2
(fused SUBS/B.cc loop)
Result (median cycles for code): 1.0035
| retire uop (01) | cycle (02) | 03 | 1e | 1f | 3f | 4d | 51 | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | 60 | 69 | 6a | 6b | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | 9f | l1d cache writeback (a8) | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10204 | 10035 | 75 | 45 | 88 | 61 | 9877 | 25 | 10166 | 10100 | 10100 | 88664 | 1 | 49 | 7001 | 0 | 10035 | 10035 | 8584 | 3 | 8722 | 10100 | 10200 | 10200 | 10035 | 41 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 100 | 1 | 0 | 710 | 1 | 37 | 1 | 1 | 9941 | 10000 | 10100 | 10036 | 10036 | 10036 | 10036 | 10036 |
| 10204 | 10035 | 75 | 153 | 0 | 61 | 9877 | 25 | 10100 | 10100 | 10100 | 88664 | 0 | 49 | 6955 | 0 | 10035 | 10035 | 8580 | 3 | 8722 | 10100 | 10200 | 10200 | 10035 | 41 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 100 | 0 | 3 | 710 | 1 | 37 | 1 | 1 | 9941 | 10000 | 10100 | 10036 | 10036 | 10036 | 10036 | 10036 |
| 10204 | 10035 | 75 | 0 | 0 | 61 | 9877 | 25 | 10100 | 10100 | 10100 | 88664 | 1 | 49 | 6955 | 0 | 10035 | 10072 | 8580 | 3 | 8722 | 10100 | 10200 | 10200 | 10035 | 41 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 100 | 1 | 0 | 710 | 1 | 37 | 1 | 1 | 9941 | 10000 | 10100 | 10036 | 10036 | 10036 | 10036 | 10036 |
| 10204 | 10035 | 75 | 0 | 0 | 61 | 9877 | 25 | 10100 | 10100 | 10100 | 88664 | 1 | 49 | 6955 | 0 | 10035 | 10035 | 8580 | 3 | 8722 | 10100 | 10200 | 10200 | 10035 | 41 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 100 | 1 | 0 | 710 | 1 | 37 | 1 | 1 | 9941 | 10000 | 10100 | 10036 | 10036 | 10036 | 10036 | 10036 |
| 10204 | 10035 | 75 | 0 | 0 | 61 | 9877 | 25 | 10100 | 10100 | 10100 | 88664 | 0 | 49 | 6955 | 0 | 10035 | 10035 | 8580 | 3 | 8722 | 10100 | 10200 | 10200 | 10035 | 41 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 100 | 0 | 0 | 710 | 1 | 37 | 1 | 1 | 9941 | 10000 | 10100 | 10036 | 10036 | 10036 | 10036 | 10036 |
| 10204 | 10035 | 75 | 0 | 0 | 61 | 9877 | 25 | 10100 | 10100 | 10100 | 88664 | 0 | 49 | 6955 | 0 | 10035 | 10035 | 8580 | 3 | 8722 | 10100 | 10200 | 10200 | 10035 | 41 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 100 | 1 | 6 | 710 | 1 | 37 | 1 | 1 | 9941 | 10000 | 10100 | 10036 | 10036 | 10036 | 10036 | 10036 |
| 10204 | 10035 | 75 | 0 | 0 | 103 | 9877 | 25 | 10100 | 10100 | 10100 | 88664 | 0 | 49 | 6955 | 0 | 10035 | 10035 | 8580 | 3 | 8722 | 10100 | 10200 | 10200 | 10035 | 41 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 100 | 0 | 0 | 710 | 1 | 37 | 1 | 1 | 9941 | 10000 | 10100 | 10036 | 10036 | 10036 | 10036 | 10036 |
| 10204 | 10035 | 75 | 0 | 0 | 61 | 9877 | 25 | 10100 | 10100 | 10100 | 88664 | 0 | 49 | 6955 | 0 | 10035 | 10035 | 8580 | 3 | 8722 | 10100 | 10200 | 10200 | 10035 | 41 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 100 | 0 | 0 | 710 | 1 | 37 | 1 | 1 | 9941 | 10000 | 10100 | 10036 | 10036 | 10036 | 10036 | 10036 |
| 10204 | 10035 | 75 | 0 | 0 | 536 | 9877 | 25 | 10100 | 10100 | 10100 | 88664 | 0 | 49 | 6955 | 0 | 10035 | 10035 | 8580 | 3 | 8722 | 10100 | 10200 | 10200 | 10035 | 41 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 100 | 0 | 0 | 710 | 1 | 37 | 1 | 1 | 9941 | 10000 | 10100 | 10036 | 10036 | 10036 | 10036 | 10036 |
| 10204 | 10035 | 75 | 0 | 0 | 61 | 9877 | 25 | 10100 | 10100 | 10100 | 88664 | 0 | 49 | 6955 | 0 | 10035 | 10035 | 8580 | 3 | 8722 | 10100 | 10200 | 10200 | 10035 | 41 | 1 | 1 | 10201 | 100 | 99 | 100 | 10100 | 100 | 0 | 0 | 710 | 1 | 37 | 1 | 1 | 9941 | 10000 | 10100 | 10036 | 10036 | 10036 | 10036 | 10036 |
Result (median cycles for code): 1.0035
| retire uop (01) | cycle (02) | 03 | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 3f | 4d | 51 | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | 9f | l1d tlb miss (a1) | l1d cache writeback (a8) | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 10024 | 10035 | 75 | 0 | 0 | 0 | 24 | 0 | 61 | 9863 | 25 | 10010 | 10010 | 10010 | 88784 | 0 | 49 | 6955 | 10035 | 10035 | 8602 | 3 | 8740 | 10010 | 10020 | 10020 | 10035 | 41 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10 | 0 | 0 | 0 | 640 | 3 | 41 | 3 | 3 | 9940 | 10000 | 10010 | 10036 | 10036 | 10036 | 10036 | 10036 |
| 10024 | 10035 | 75 | 0 | 0 | 0 | 0 | 0 | 61 | 9863 | 25 | 10010 | 10010 | 10010 | 88784 | 0 | 49 | 6955 | 10035 | 10035 | 8602 | 3 | 8740 | 10010 | 10020 | 10020 | 10035 | 41 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10 | 0 | 0 | 0 | 640 | 3 | 41 | 3 | 3 | 9940 | 10000 | 10010 | 10036 | 10036 | 10036 | 10036 | 10036 |
| 10024 | 10035 | 75 | 0 | 0 | 0 | 0 | 0 | 61 | 9863 | 25 | 10010 | 10010 | 10010 | 88784 | 0 | 49 | 6955 | 10035 | 10035 | 8602 | 3 | 8740 | 10010 | 10020 | 10020 | 10035 | 41 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10 | 0 | 0 | 0 | 640 | 3 | 41 | 3 | 3 | 9940 | 10000 | 10010 | 10036 | 10036 | 10036 | 10036 | 10036 |
| 10024 | 10035 | 75 | 0 | 0 | 0 | 0 | 0 | 61 | 9863 | 25 | 10010 | 10010 | 10010 | 88784 | 0 | 49 | 6955 | 10035 | 10035 | 8602 | 3 | 8740 | 10010 | 10020 | 10020 | 10035 | 41 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10 | 0 | 0 | 0 | 640 | 3 | 41 | 3 | 3 | 9940 | 10000 | 10010 | 10036 | 10036 | 10036 | 10036 | 10036 |
| 10024 | 10035 | 75 | 0 | 0 | 0 | 0 | 0 | 61 | 9863 | 25 | 10010 | 10010 | 10010 | 88784 | 0 | 49 | 6955 | 10035 | 10035 | 8602 | 3 | 8740 | 10010 | 10020 | 10020 | 10035 | 41 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10 | 0 | 0 | 0 | 640 | 3 | 41 | 3 | 3 | 9940 | 10000 | 10010 | 10036 | 10036 | 10036 | 10036 | 10036 |
| 10024 | 10035 | 75 | 0 | 0 | 0 | 0 | 0 | 61 | 9863 | 25 | 10010 | 10010 | 10010 | 88784 | 0 | 49 | 6955 | 10035 | 10035 | 8602 | 3 | 8740 | 10010 | 10020 | 10020 | 10035 | 41 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10 | 0 | 0 | 0 | 640 | 3 | 41 | 3 | 3 | 9940 | 10000 | 10010 | 10036 | 10036 | 10036 | 10036 | 10036 |
| 10024 | 10035 | 75 | 0 | 0 | 0 | 0 | 0 | 61 | 9863 | 25 | 10010 | 10010 | 10010 | 88784 | 0 | 49 | 6955 | 10035 | 10035 | 8602 | 3 | 8740 | 10010 | 10020 | 10020 | 10035 | 41 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10 | 0 | 0 | 0 | 640 | 3 | 41 | 3 | 3 | 9940 | 10000 | 10010 | 10036 | 10036 | 10036 | 10036 | 10036 |
| 10024 | 10035 | 75 | 0 | 0 | 0 | 273 | 0 | 61 | 9863 | 25 | 10010 | 10010 | 10010 | 88784 | 0 | 49 | 6955 | 10035 | 10035 | 8602 | 3 | 8740 | 10010 | 10020 | 10020 | 10035 | 41 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10 | 0 | 0 | 0 | 640 | 3 | 41 | 3 | 3 | 9940 | 10000 | 10010 | 10036 | 10036 | 10036 | 10036 | 10036 |
| 10024 | 10035 | 75 | 0 | 0 | 1 | 0 | 0 | 103 | 9863 | 25 | 10010 | 10010 | 10010 | 88784 | 1 | 49 | 6955 | 10035 | 10035 | 8602 | 3 | 8740 | 10167 | 10020 | 10020 | 10035 | 41 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10 | 0 | 0 | 0 | 640 | 3 | 41 | 3 | 3 | 9940 | 10000 | 10010 | 10036 | 10036 | 10036 | 10036 | 10036 |
| 10024 | 10035 | 75 | 1 | 0 | 0 | 0 | 0 | 61 | 9863 | 25 | 10010 | 10010 | 10010 | 88784 | 0 | 49 | 6955 | 10035 | 10035 | 8602 | 3 | 8740 | 10010 | 10020 | 10020 | 10035 | 41 | 1 | 1 | 10021 | 10 | 9 | 10 | 10010 | 10 | 0 | 0 | 3 | 662 | 3 | 41 | 3 | 3 | 9940 | 10000 | 10010 | 10036 | 10036 | 10036 | 10036 | 10036 |
Count: 8
Code:
ubfiz x0, x8, #3, #7 ubfiz x1, x8, #3, #7 ubfiz x2, x8, #3, #7 ubfiz x3, x8, #3, #7 ubfiz x4, x8, #3, #7 ubfiz x5, x8, #3, #7 ubfiz x6, x8, #3, #7 ubfiz x7, x8, #3, #7
mov x8, 9
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.1674
| retire uop (01) | cycle (02) | 03 | mmu table walk instruction (07) | l2 tlb miss instruction (0a) | l2 tlb miss data (0b) | 1e | 3f | 51 | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | 9f | l1d tlb miss (a1) | ld unit uop (a6) | l1d cache writeback (a8) | ac | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80204 | 13413 | 100 | 1 | 1 | 0 | 12 | 28 | 27 | 80136 | 80136 | 80148 | 400710 | 1 | 49 | 10310 | 13390 | 13390 | 3326 | 6 | 3336 | 80148 | 80264 | 80264 | 13390 | 39 | 1 | 1 | 80201 | 100 | 99 | 100 | 80100 | 100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5119 | 1 | 16 | 1 | 1 | 13387 | 80036 | 80100 | 13391 | 13391 | 13391 | 13391 | 13391 |
| 80204 | 13390 | 100 | 1 | 1 | 0 | 0 | 28 | 27 | 80136 | 80136 | 80148 | 400710 | 0 | 49 | 10310 | 13390 | 13390 | 3326 | 6 | 3336 | 80148 | 80264 | 80264 | 13390 | 39 | 1 | 1 | 80201 | 100 | 99 | 100 | 80100 | 100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5119 | 1 | 16 | 1 | 1 | 13387 | 80036 | 80100 | 13391 | 13391 | 13391 | 13391 | 13391 |
| 80204 | 13390 | 101 | 1 | 1 | 0 | 0 | 28 | 27 | 80136 | 80136 | 80148 | 400710 | 1 | 49 | 10310 | 13390 | 13390 | 3326 | 6 | 3336 | 80148 | 80264 | 80264 | 13390 | 39 | 1 | 1 | 80201 | 100 | 99 | 100 | 80100 | 100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5119 | 1 | 16 | 1 | 1 | 13387 | 80036 | 80100 | 13391 | 13391 | 13391 | 13391 | 13391 |
| 80204 | 13390 | 100 | 1 | 1 | 1 | 66 | 28 | 27 | 80136 | 80136 | 80148 | 400710 | 1 | 49 | 10310 | 13390 | 13390 | 3326 | 6 | 3336 | 80148 | 80264 | 80264 | 13390 | 39 | 1 | 1 | 80201 | 100 | 99 | 100 | 80100 | 100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5119 | 1 | 16 | 1 | 1 | 13387 | 80036 | 80100 | 13391 | 13391 | 13391 | 13391 | 13391 |
| 80204 | 13390 | 100 | 1 | 1 | 0 | 75 | 28 | 27 | 80136 | 80136 | 80148 | 400710 | 0 | 49 | 10310 | 13390 | 13390 | 3326 | 6 | 3336 | 80148 | 80264 | 80264 | 13390 | 39 | 1 | 1 | 80201 | 100 | 99 | 100 | 80100 | 100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5119 | 1 | 16 | 1 | 1 | 13387 | 80036 | 80100 | 13391 | 13391 | 13391 | 13391 | 13391 |
| 80204 | 13390 | 101 | 1 | 1 | 0 | 0 | 28 | 27 | 80136 | 80136 | 80148 | 400710 | 0 | 49 | 10310 | 13390 | 13390 | 3326 | 6 | 3336 | 80148 | 80264 | 80264 | 13390 | 39 | 2 | 1 | 80201 | 100 | 99 | 100 | 80100 | 100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5119 | 1 | 16 | 1 | 1 | 13387 | 80036 | 80100 | 13391 | 13391 | 13391 | 13391 | 13391 |
| 80204 | 13390 | 100 | 1 | 1 | 0 | 0 | 28 | 27 | 80136 | 80136 | 80148 | 400710 | 1 | 49 | 10310 | 13390 | 13390 | 3326 | 6 | 3336 | 80148 | 80264 | 80264 | 13390 | 39 | 1 | 1 | 80201 | 100 | 99 | 100 | 80100 | 100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5119 | 1 | 16 | 1 | 1 | 13387 | 80036 | 80100 | 13391 | 13391 | 13391 | 13391 | 13391 |
| 80204 | 13390 | 100 | 1 | 1 | 0 | 0 | 28 | 27 | 80136 | 80136 | 80148 | 400710 | 0 | 49 | 10310 | 13390 | 13390 | 3326 | 6 | 3336 | 80148 | 80264 | 80264 | 13390 | 39 | 1 | 1 | 80201 | 100 | 99 | 100 | 80100 | 100 | 0 | 0 | 1 | 9 | 1 | 1 | 1 | 5119 | 1 | 16 | 1 | 1 | 13387 | 80036 | 80100 | 13391 | 13391 | 13391 | 13391 | 13391 |
| 80204 | 13390 | 100 | 1 | 1 | 0 | 0 | 28 | 27 | 80136 | 80136 | 80148 | 400710 | 0 | 49 | 10310 | 13390 | 13390 | 3326 | 6 | 3336 | 80148 | 80264 | 80264 | 13390 | 39 | 1 | 1 | 80201 | 100 | 99 | 100 | 80100 | 100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5119 | 1 | 16 | 1 | 1 | 13387 | 80036 | 80100 | 13391 | 13391 | 13391 | 13391 | 13391 |
| 80204 | 13390 | 100 | 1 | 1 | 0 | 0 | 28 | 27 | 80136 | 80136 | 80148 | 400710 | 1 | 49 | 10310 | 13390 | 13390 | 3326 | 6 | 3336 | 80148 | 80264 | 80264 | 13390 | 39 | 1 | 1 | 80201 | 100 | 99 | 100 | 80100 | 100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 5119 | 1 | 16 | 1 | 1 | 13387 | 80036 | 80100 | 13391 | 13391 | 13391 | 13391 | 13391 |
Result (median cycles for code divided by count): 0.1671
| retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 18 | 19 | 1e | 3f | 51 | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | 5f | 60 | 69 | 6a | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | 9f | l1d cache writeback (a8) | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
| 80024 | 13387 | 100 | 0 | 0 | 0 | 0 | 35 | 25 | 80010 | 80010 | 80010 | 400050 | 4 | 1 | 49 | 10291 | 13371 | 13371 | 3330 | 3 | 3348 | 80010 | 80020 | 80020 | 13371 | 39 | 1 | 1 | 80021 | 10 | 9 | 10 | 80010 | 10 | 0 | 0 | 0 | 0 | 5021 | 7 | 19 | 2 | 4 | 13368 | 80000 | 80010 | 13372 | 13372 | 13372 | 13372 | 13372 |
| 80024 | 13371 | 100 | 0 | 0 | 0 | 0 | 35 | 25 | 80010 | 80010 | 80010 | 400050 | 7 | 1 | 49 | 10291 | 13371 | 13371 | 3330 | 3 | 3348 | 80010 | 80020 | 80020 | 13371 | 39 | 1 | 1 | 80021 | 10 | 9 | 10 | 80010 | 10 | 0 | 0 | 0 | 0 | 5022 | 4 | 19 | 2 | 4 | 13368 | 80000 | 80010 | 13372 | 13372 | 13372 | 13372 | 13372 |
| 80024 | 13371 | 100 | 0 | 0 | 0 | 0 | 35 | 25 | 80010 | 80010 | 80010 | 400050 | 7 | 1 | 49 | 10291 | 13371 | 13371 | 3330 | 3 | 3348 | 80010 | 80020 | 80020 | 13371 | 39 | 1 | 1 | 80021 | 10 | 9 | 10 | 80010 | 10 | 0 | 0 | 0 | 0 | 5022 | 4 | 19 | 4 | 2 | 13368 | 80000 | 80010 | 13372 | 13372 | 13372 | 13372 | 13372 |
| 80024 | 13371 | 100 | 0 | 1 | 2 | 0 | 35 | 25 | 80010 | 80010 | 80010 | 400050 | 7 | 1 | 49 | 10291 | 13371 | 13371 | 3330 | 3 | 3348 | 80010 | 80020 | 80020 | 13371 | 39 | 1 | 1 | 80021 | 10 | 9 | 10 | 80010 | 10 | 0 | 0 | 0 | 0 | 5042 | 4 | 19 | 2 | 4 | 13368 | 80000 | 80010 | 13372 | 13372 | 13372 | 13372 | 13372 |
| 80024 | 13371 | 100 | 0 | 0 | 0 | 0 | 35 | 25 | 80010 | 80010 | 80010 | 400050 | 9 | 1 | 49 | 10291 | 13371 | 13371 | 3330 | 3 | 3348 | 80010 | 80020 | 80020 | 13371 | 39 | 1 | 1 | 80021 | 10 | 9 | 10 | 80010 | 10 | 0 | 0 | 0 | 0 | 5021 | 2 | 19 | 2 | 6 | 13368 | 80000 | 80010 | 13372 | 13372 | 13372 | 13372 | 13372 |
| 80024 | 13371 | 100 | 0 | 0 | 0 | 0 | 35 | 25 | 80010 | 80010 | 80010 | 400050 | 8 | 1 | 49 | 10291 | 13371 | 13371 | 3330 | 3 | 3348 | 80010 | 80020 | 80020 | 13371 | 39 | 1 | 1 | 80021 | 10 | 9 | 10 | 80010 | 10 | 0 | 0 | 0 | 0 | 5022 | 4 | 19 | 4 | 2 | 13368 | 80000 | 80010 | 13372 | 13372 | 13372 | 13372 | 13372 |
| 80024 | 13371 | 100 | 0 | 0 | 0 | 0 | 35 | 25 | 80010 | 80010 | 80010 | 400050 | 7 | 1 | 49 | 10291 | 13371 | 13371 | 3330 | 3 | 3348 | 80010 | 80020 | 80020 | 13371 | 39 | 1 | 1 | 80021 | 10 | 9 | 10 | 80010 | 10 | 0 | 0 | 0 | 0 | 5022 | 4 | 19 | 4 | 2 | 13368 | 80000 | 80010 | 13372 | 13372 | 13372 | 13372 | 13372 |
| 80024 | 13371 | 100 | 0 | 0 | 0 | 0 | 35 | 25 | 80010 | 80010 | 80010 | 400050 | 8 | 1 | 49 | 10291 | 13371 | 13371 | 3330 | 3 | 3348 | 80010 | 80020 | 80020 | 13371 | 39 | 1 | 1 | 80021 | 10 | 9 | 10 | 80010 | 10 | 0 | 0 | 0 | 0 | 5022 | 4 | 19 | 4 | 2 | 13368 | 80000 | 80010 | 13372 | 13372 | 13372 | 13372 | 13372 |
| 80024 | 13371 | 100 | 0 | 0 | 0 | 0 | 35 | 25 | 80010 | 80010 | 80010 | 400050 | 8 | 1 | 49 | 10291 | 13371 | 13371 | 3330 | 3 | 3348 | 80010 | 80020 | 80020 | 13371 | 39 | 1 | 1 | 80021 | 10 | 9 | 10 | 80010 | 10 | 0 | 0 | 0 | 0 | 5021 | 2 | 19 | 2 | 4 | 13368 | 80000 | 80010 | 13372 | 13372 | 13372 | 13372 | 13372 |
| 80024 | 13371 | 100 | 0 | 0 | 0 | 0 | 35 | 25 | 80010 | 80010 | 80010 | 400050 | 8 | 1 | 49 | 10291 | 13371 | 13371 | 3330 | 3 | 3348 | 80010 | 80020 | 80020 | 13371 | 39 | 1 | 1 | 80021 | 10 | 9 | 10 | 80010 | 10 | 0 | 1 | 0 | 0 | 5022 | 4 | 19 | 2 | 4 | 13368 | 80000 | 80010 | 13372 | 13372 | 13372 | 13372 | 13372 |