Firestorm: NGCS (register, 64-bit) measurements

Code:

  ngcs x0, x0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	2	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	2	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1	1035	1035	805	3	882	1000	1000	2000	1035	40	1	1	1001	1000	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036

Test 2: Latency 1->2

Code:

  ngcs x0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	76	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	0	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	1	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	441	9920	25	10100	10100	10100	647152	1	49	6955	0	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	0	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	3	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	0	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	0	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	76	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	0	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	1	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	0	49	6955	0	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10195	10100	10100	647152	0	49	6955	0	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	1	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	0	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	1	3	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	61	9920	25	10100	10100	10100	647152	1	49	6955	0	10035	10035	8656	3	8732	10100	10200	20200	10035	40	1	1	10201	100	99	100	10100	100	0	1	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	76	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	4	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	1	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10094	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	1101	9918	25	10010	10035	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	49	6955	10035	10035	8678	3	8754	10010	10020	20020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036

Test 3: Latency 1->3

Chain cycles: 1

Code:

  ngcs x0, x1
  tst x0, 1

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	0	1506	19926	25	20200	20200	20200	1297650	49	16955	0	20035	20035	17406	3	17481	20200	20200	30200	20035	64	1	1	20201	100	99	20100	0	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19926	25	20200	20200	20200	1297650	49	16955	0	20035	20035	17406	3	17481	20200	20200	30200	20035	64	1	1	20201	100	99	20100	0	0	0	0	1310	1	28	1	1	20002	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	82	19926	25	20200	20200	20200	1297650	49	16955	0	20035	20035	17406	3	17481	20200	20200	30200	20035	64	1	1	20201	100	99	20100	0	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	747	19926	25	20200	20200	20200	1297650	49	16955	0	20035	20035	17406	3	17481	20200	20200	30200	20035	64	1	1	20201	100	99	20100	0	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19926	25	20200	20200	20200	1298277	49	16955	0	20035	20035	17406	3	17481	20200	20200	30200	20035	64	1	1	20201	100	99	20100	0	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	149	0	147	19926	25	20222	20200	20200	1297650	49	16955	0	20035	20035	17406	3	17481	20200	20200	30200	20035	64	1	1	20201	100	99	20100	0	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	145	19926	25	20200	20200	20200	1297650	49	16955	0	20035	20035	17406	3	17481	20200	20200	30200	20035	64	1	1	20201	100	99	20100	0	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	208	19926	25	20200	20200	20200	1297650	49	16955	0	20035	20035	17406	3	17481	20200	20200	30200	20035	64	1	1	20201	100	99	20100	0	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19926	25	20200	20200	20200	1297650	49	16955	0	20035	20035	17406	3	17481	20200	20200	30200	20035	64	1	1	20201	100	99	20100	0	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	61	19926	25	20200	20200	20200	1297650	49	16955	0	20035	20035	17406	3	17481	20200	20200	30200	20035	64	1	1	20201	100	99	20100	0	0	1	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	0	0	0	0	0	0	689	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	30020	20035	64	1	1	20021	10	9	20010	0	0	0	0	1	0	0	0	1270	2	27	1	1	19995	20032	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	61	19918	25	20020	20020	20020	1297297	49	16955	20081	20035	17428	3	17504	20020	20020	30020	20035	64	1	1	20021	10	9	20010	0	0	0	0	0	0	3	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	82	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	30020	20035	64	1	1	20021	10	9	20010	0	0	0	0	0	0	18	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	82	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	30020	20035	64	1	1	20021	10	9	20010	0	0	2	0	0	0	0	0	1270	2	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	61	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	30020	20035	64	1	1	20021	10	9	20010	0	0	0	0	1	0	0	0	1270	2	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	61	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	30020	20035	64	1	1	20021	10	9	20010	0	0	0	0	0	0	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	61	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	30020	20035	64	1	1	20021	10	9	20010	0	0	0	0	0	0	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	147	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	30020	20035	64	1	1	20021	10	9	20010	0	2	0	0	0	0	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	12	0	0	61	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	30020	20080	64	1	1	20021	10	9	20010	0	2	0	0	1	0	0	0	1270	2	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	61	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	30020	20035	64	1	1	20021	10	9	20010	0	0	0	0	0	0	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036

Test 4: Latency 3->2

Chain cycles: 1

Code:

  ngcs x0, x1
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	0	0	0	0	2870	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	1	1	1	1319	0	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	1	1	1	1319	1	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	1	1	1	1320	0	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	1	1	1	1320	0	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	149	0	0	0	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	1	1	1	1319	0	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	147	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	8	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	1	1	1	1319	0	16	20012	20000	20100	20068	20036	20036	20036	20036
20204	20035	150	0	0	0	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	3	0	1	1	1	1320	0	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	8	17485	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	1	1	1	1320	0	16	20032	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	61	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	7	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	1	1	1	1320	0	16	20012	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	156	19930	25	20100	20100	20112	1297233	0	49	16955	20035	20035	17425	8	17486	20112	20224	30236	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	1	1	1	1319	0	16	20012	20000	20100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	94	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	2	27	2	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	1165	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	2	27	2	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	103	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	2	27	1	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	2	27	2	1	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	170	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	2	27	1	1	19995	20000	20010	20036	20036	20068	20036	20036
20024	20035	149	272	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	6	27	2	1	19995	20000	20010	20067	20036	20036	20036	20036
20024	20035	150	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	61	19918	25	20010	20010	20010	1297247	0	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1270	1	27	1	1	19995	20000	20010	20036	20036	20036	20036	20036

Test 5: Latency 3->3

Code:

  ngcs x0, x1

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	61	9927	25	10200	10200	10210	647712	1	49	6955	10035	10035	8673	8	8735	10210	10224	20248	10035	40	1	1	10201	100	99	10100	0	0	0	0	1	1	1	720	16	0	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9927	25	10200	10200	10210	647712	1	49	6955	10035	10035	8673	8	8735	10210	10224	20248	10035	40	1	1	10201	100	99	10100	0	0	0	0	1	1	1	720	16	0	10012	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9927	25	10200	10200	10210	647712	0	49	6955	10035	10035	8673	8	8735	10210	10224	20248	10035	40	1	1	10201	100	99	10100	0	0	0	0	1	1	1	720	16	0	10013	10100	10100	10036	10036	10036	10036	10082
10204	10035	75	0	212	9927	25	10200	10200	10210	647712	1	49	6955	10082	10035	8673	8	8736	10210	10224	20248	10035	40	1	1	10201	100	99	10100	0	1	0	0	1	1	1	720	16	0	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9927	25	10200	10200	10210	647712	1	49	6955	10035	10035	8673	8	8735	10210	10224	20248	10035	40	1	1	10201	100	99	10100	0	0	0	0	1	1	1	720	16	0	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	76	0	61	9927	25	10200	10200	10210	647712	1	49	6955	10035	10035	8673	8	8735	10210	10224	20248	10035	40	1	1	10201	100	99	10100	0	0	0	0	1	1	1	720	16	0	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9927	25	10200	10200	10210	647712	1	49	6955	10035	10035	8673	8	8735	10210	10224	20248	10035	40	1	1	10201	100	99	10100	0	0	0	0	1	1	1	720	16	0	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9927	25	10200	10200	10210	647712	0	49	6955	10035	10035	8673	8	8735	10210	10224	20248	10035	40	1	1	10201	100	99	10100	0	0	0	0	1	1	1	720	16	0	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	189	9927	25	10200	10200	10210	647712	0	49	6955	10035	10035	8673	8	8735	10210	10224	20248	10035	40	1	1	10201	100	99	10100	0	1	0	0	1	1	1	720	16	0	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9927	25	10200	10200	10210	647712	0	49	6956	10035	10035	8673	8	8736	10210	10224	20248	10035	40	1	1	10201	100	99	10100	0	0	0	0	1	1	1	720	16	0	10013	10100	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	st unit uop (a7)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	0	61	9918	25	10020	10020	10020	647296	1	49	6955	10035	10035	8678	3	8754	10020	10020	20020	10035	40	1	1	10021	10	9	10010	0	0	0	640	2	27	2	2	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10020	10020	10020	647296	1	49	6955	10035	10035	8678	3	8754	10020	10020	20020	10035	40	1	1	10021	10	9	10010	0	0	3	640	2	27	3	2	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10020	10020	10020	647296	1	49	6955	10035	10035	8678	3	8754	10020	10020	20020	10035	40	1	1	10021	10	9	10010	0	0	0	640	2	27	3	2	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10020	10020	10020	647296	1	49	6955	10035	10035	8678	3	8754	10020	10020	20020	10035	40	1	1	10021	10	9	10010	0	0	0	640	2	27	2	2	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10020	10020	10020	647296	1	49	6955	10035	10035	8678	3	8754	10020	10020	20020	10035	40	1	1	10021	10	9	10010	0	0	0	640	2	27	2	2	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10020	10020	10020	647296	1	49	6955	10035	10035	8678	3	8754	10020	10020	20020	10035	40	1	1	10021	10	9	10010	0	0	0	640	2	27	3	2	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10020	10020	10020	647296	1	49	6956	10035	10035	8678	3	8754	10020	10020	20020	10035	40	1	1	10021	10	9	10010	0	0	0	640	3	27	2	2	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10020	10020	10020	647296	1	49	6955	10035	10035	8678	3	8754	10020	10020	20020	10035	40	1	1	10021	10	9	10010	0	0	0	640	2	27	2	2	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10020	10020	10020	647296	1	49	6955	10035	10035	8678	3	8754	10020	10020	20020	10035	40	1	1	10021	10	9	10010	0	0	0	640	3	27	2	4	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	61	9918	25	10020	10020	10020	647296	1	49	6955	10035	10035	8678	3	8754	10020	10020	20020	10035	40	1	1	10021	10	9	10010	1	0	0	640	2	27	2	2	9997	10010	10010	10036	10036	10036	10036	10036

Test 6: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  ngcs x0, x8
  ands xzr, xzr, xzr
  ngcs x1, x8
  ands xzr, xzr, xzr
  ngcs x2, x8
  ands xzr, xzr, xzr
  ngcs x3, x8
  ands xzr, xzr, xzr
  ngcs x4, x8
  ands xzr, xzr, xzr
  ngcs x5, x8
  ands xzr, xzr, xzr
  ngcs x6, x8
  ands xzr, xzr, xzr
  ngcs x7, x8

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
160204	53442	400	0	0	12	37	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	0	3	33359	160100	160200	160200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	0	0	10110	0	2	19	2	2	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	12	37	25	160100	160100	160100	1063588	1	49	50324	53404	53404	33339	0	3	33359	160100	160200	160200	53404	52	1	1	160201	100	99	100	160100	100	0	0	2	0	0	10110	0	2	19	2	2	53477	160278	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	37	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	0	3	33359	160100	160200	160200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	0	0	10110	2	4	19	2	2	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	37	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	0	3	33359	160100	160200	160200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	0	0	10110	0	2	19	2	2	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	37	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	0	3	33359	160100	160200	160200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	0	0	10110	0	2	19	4	2	53439	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	1	0	0	57	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	0	3	33359	160100	160200	160200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	0	0	10110	0	4	19	2	2	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	37	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	0	3	33359	160100	160200	160200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	0	0	10110	0	2	19	2	2	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	37	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	0	3	33359	160100	160200	160200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	0	0	10110	0	2	19	2	2	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	689	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	0	3	33359	160100	160200	160200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	0	0	10110	0	2	19	2	2	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	37	25	160100	160100	160100	1063588	0	49	50324	53404	53404	33339	0	3	33359	160100	160200	160200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	0	0	10110	0	3	19	2	4	53401	160000	80100	53405	53405	53405	53405	53405

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6672

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? int retires (ef)	f5	f6	f7	f8	fd
160024	53390	400	1	1	0	1	1	177	91	25	160010	160010	160010	1029388	1	1	10	49	50294	53374	53374	33331	3	33351	160010	160020	160020	53374	52	1	1	160021	10	9	10	160010	10	0	3	0	0	10022	13	52	3	20	19	2	1	1	20	22	53370	160000	20	11	80010	53375	53375	53375	53375	53375
160024	53374	399	0	0	0	0	0	0	85	25	160010	160010	160010	1029388	1	1	10	49	50294	53374	53374	33331	3	33351	160010	160020	160020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	10022	13	47	3	28	19	2	1	1	18	20	53370	160000	20	11	80010	53375	53375	53375	53375	53375
160024	53374	399	0	0	0	0	0	33	43	25	160010	160010	160010	1029388	1	1	10	49	50294	53374	53374	33331	3	33351	160010	160020	160020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	10022	13	54	3	18	19	1	1	1	15	20	53370	160000	21	11	80010	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	0	0	43	25	160010	160010	160010	1029388	1	1	10	49	50294	53374	53374	33331	3	33351	160010	160020	160020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	10022	13	67	3	19	19	2	1	1	19	21	53370	160000	21	11	80010	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	0	0	43	25	160010	160010	160010	1029388	1	1	10	49	50294	53374	53374	33331	3	33351	160010	160020	160020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	10022	13	63	3	18	19	2	1	1	21	17	53370	160000	20	11	80010	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	0	0	43	25	160010	160010	160010	1029388	1	1	10	49	50294	53374	53374	33331	3	33351	160010	160020	160020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	10022	13	61	3	31	19	2	1	1	20	18	53370	160000	21	11	80010	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	0	0	6844	25	160010	160010	160010	1029388	1	1	10	49	50294	53374	53374	33331	3	33351	160010	160020	160020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	10022	13	52	3	17	19	2	1	1	19	21	53370	160000	21	11	80010	53375	53375	53375	53375	53375
160024	53374	400	1	1	1	0	0	0	43	25	160010	160010	160010	1029388	1	1	10	49	50294	53374	53374	33331	3	33351	160010	160020	160020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	10022	13	51	3	20	19	1	1	1	17	20	53370	160000	21	11	80010	53375	53375	53375	53375	53375
160024	53374	400	0	0	0	0	0	0	43	25	160010	160010	160010	1029388	1	1	10	49	50294	53374	53374	33331	3	33351	160010	160020	160020	53374	52	1	1	160021	10	9	10	160010	10	0	0	1	0	10022	13	53	3	20	19	2	1	1	19	21	53370	160000	21	11	80010	53375	53375	53375	53375	53375
160024	53374	399	0	0	0	0	0	0	43	25	160010	160010	160010	1029388	1	1	10	49	50294	53374	53374	33331	3	33351	160010	160020	160020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	10022	13	50	3	26	19	2	1	1	19	20	53370	160000	20	11	80010	53375	53375	53375	53375	53375

Test 7: throughput

Count: 4

Code:

  fcmp s0, s0
  ngcs x0, x4
  ngcs x1, x4
  ngcs x2, x4
  ngcs x3, x4

Initialization

  mov x4, 5
  mov x5, 6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3353

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss data (0b)	18	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
50204	13464	100	0	0	0	0	45	25	50100	40100	10000	40100	10000	587442	80000	1	13383	13412	13412	5538	3081	3	7117	50100	40200	10000	80200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	3210	2	19	2	4	13408	40000	40100	13413	13413	13490	13413	13413
50204	13476	101	0	0	0	135	45	45	50100	40100	10000	40100	10000	574746	80000	1	13383	13412	13412	6026	3342	3	7117	50100	40200	10000	80200	20000	13472	13412	1	1	50201	100	99	100	40100	10000	100	2	0	0	0	3210	2	34	2	2	13408	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	0	0	12	45	25	50100	40100	10000	40100	10000	574746	80000	1	13383	13412	13412	6026	3342	3	7117	50100	40200	10000	80200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	3210	3	19	2	2	13409	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	0	0	0	66	25	50100	40100	10000	40100	10000	587442	80000	1	13383	13412	13412	6026	3342	3	7117	50100	40200	10000	80200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	3210	2	19	2	2	13409	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	0	0	0	45	25	50125	40100	10000	40100	10000	587442	80000	1	13383	13412	13420	6026	2446	3	7117	50100	40200	10000	80200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	3212	2	19	2	2	13408	40000	40100	13421	13421	13413	13413	13413
50204	13412	100	1	0	0	0	45	25	50100	40125	10000	40100	10000	587442	80000	1	13391	13412	13420	6103	2444	3	7125	50125	40200	10000	80200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	1	3	0	3210	4	19	4	4	13409	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	0	0	0	45	25	50100	40100	10000	40100	10000	574746	80000	1	13383	13412	13412	6026	3353	3	7117	50100	40200	10000	80200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	3	0	3210	2	19	6	2	13417	40000	40100	13413	13413	13413	13413	13413
50204	13412	101	0	0	0	0	45	25	50100	40100	10000	40100	10000	574746	80000	1	13383	13473	13474	5553	3081	3	7117	50100	40200	10026	80200	20000	13420	13420	1	1	50201	100	99	100	40100	10000	100	0	0	6	2	3210	2	19	3	2	13408	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	0	0	0	45	25	50100	40100	10000	40100	10000	574746	80000	1	13383	13420	13412	5553	2421	3	7125	50100	40200	10000	80200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	3210	2	19	2	2	13409	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	0	0	0	45	25	50100	40100	10000	40100	10000	574746	80000	1	13383	13412	13412	5538	3342	3	7117	50100	40200	10000	80200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	0	0	3210	2	19	2	2	13408	40000	40100	13413	13413	13413	13413	13413

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3346

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? int retires (ef)	f5	f6	f7	f8	fd
50024	13408	100	0	87	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5580	3254	3	7109	50010	40020	10000	80020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	3140	0	0	0	2	19	0	0	0	2	2	13379	40000	0	0	40010	13383	13383	13383	13383	13383
50024	13382	101	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5580	3254	3	7109	50010	40020	10000	80020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	3140	0	0	0	2	19	0	0	0	2	2	13379	40000	0	0	40010	13383	13383	13383	13383	13383
50024	13382	100	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5580	3913	3	7109	50010	40020	10000	80020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	3140	0	0	0	2	19	0	0	0	2	2	13379	40000	0	0	40010	13383	13383	13383	13383	13383
50024	13382	100	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5580	3254	3	7109	50010	40020	10000	80020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	3159	0	0	0	2	19	0	0	0	2	2	13379	40000	0	0	40010	13383	13383	13383	13383	13383
50024	13382	100	0	99	25	50010	40010	10000	40010	10000	573456	80000	1	13353	13382	13382	5951	3913	3	7109	50010	40020	10000	80020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	3140	3	0	1	4	19	2	0	1	4	3	13379	40000	0	0	40010	13383	13383	13383	13383	13383
50024	13382	100	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5580	3913	3	7109	50010	40020	10000	80020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	3142	3	1	1	4	19	0	0	0	2	2	13379	40000	0	0	40010	13383	13383	13383	13383	13383
50024	13382	100	0	45	25	50010	40010	10000	40010	10000	573456	80000	1	13353	13382	13382	5580	3913	3	7109	50010	40020	10000	80020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	3140	0	0	0	2	19	0	1	0	3	3	13379	40000	0	0	40010	13383	13383	13383	13383	13383
50024	13382	100	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5951	3254	3	7109	50010	40020	10000	80020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	3140	0	0	0	2	19	0	0	0	2	2	13379	40000	20	0	40010	13441	13383	13383	13383	13383
50024	13382	100	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5580	3254	3	7109	50010	40020	10000	80020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	3140	0	0	0	2	19	0	0	0	2	2	13379	40000	0	0	40010	13383	13383	13383	13383	13383
50024	13382	100	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5580	3913	3	7109	50010	40020	10000	80020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	3140	0	0	0	2	19	0	0	0	2	2	13379	40000	0	0	40010	13383	13383	13383	13383	13383

NGCS (register, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 7: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations