Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

DMB (LD)

Test 1: uops

Code:

  dmb ld

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)60696d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)8283flush restart other nonspec (84)85inst all (8c)inst barrier (9c)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)f5f6f7f8fd
1004302723030202000100010001000600014230353027328851000100030263035111001100010000073116113032100030273036302830363027
1004302622030202009100010001000600014230353025328851000100030253035111001100010000073116113032100030273036302830363028
1004302722030122001100010001000600014230353027328841000100030273035111001100010000073116113032100030363028303630273036
1004303522030202009100010001000600014230353027328841000100030273035111001100010000073116113023100030363027303630283036
1004303523030122009100010001000600014230353026328841000100030263035111001100010000073116113032100030363028303630283036
10043035220302020091000100010006000142303530263288410001000302630351110011000100006373116113032100030273036302730363028
1004302722030202001100010001000600013430273035328931000100030263035111001100010000073116113032100030363027303630263036
1004303523030112009100010001000600013430273035328931000100030353027111001100010000073116113024100030273036302730363028
1004302723030112009100010001000600013330273035328931000100030353027111001100010008073116113032100030363027303630283036
1004303522030112009100010001000600014230353025328851000100030253035111001100010000073116113023100030363028303630283036

Test 2: throughput

Code:

  dmb ld

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.9043

retire uop (01)cycle (02)031f3f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696a6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst barrier (9c)9fl1d tlb access (a0)st unit uop (a7)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)? int retires (ef)f5f6f7f8fd
1020429112218029120190081010010010000100100005005980014926055291352903432784310100200100002002913523214111020110099100100100001000100000007102161129031100001002913629044291362903629136
102042913521813229120189081010010010008100100005005980014925955291352902732774210100200100002002903523295111020110099100100100001000100000198507101161129025100001002903629136290452913629035
1020429586218029028189081010010010000100100005005980014926055290352913532784310100200100002002913523216111020110099100100100001000100000007101161129032100001002903529136290442913629037
1020429036218029120189171010010010000100100005005980014926055290252913532784310100200100002002913523223111020110099100100100001000100000007101161129032100001002904329136290442913629045
1020429044218029120190081010010010000100100005005980014925963291352903532773310100200100002002902723295111020110099100100100001000100000007101161129132100001002902629136290362913629029
1020429028218029020190081010010010000100100005005980014925955291352904432775110100200100002002904323295111020110099100100100001000100001007101161129132100001002913629037291362904329136
1020429135217029120189171010010010000100100005005980014925955291352904432775110100200100002002904323295111020110099100100100001000100000007101161129132100001002913629044291362903629136
1020429135218029120189081010010010000100100005005980014926055290352913532784310100200100002002913523216111020110099100100100001000100000007101161129040100001002913629043291362904429136
1020429135218029013190081010010010000100100005005980014925964291352904332774310100200100002002903423295111020110099100100100001000100000007101161129132100001002903629136290292913629036
1020429035218029120189081010010010000100100005005980014926055290352913532784310100200100002002902823295111020110099100100100001000100000007101161129132100001002913629026291362903629136

1000 unrolls and 10 iterations

Result (median cycles for code): 2.9919

retire uop (01)cycle (02)03mmu table walk data (08)191e3f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696a6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst barrier (9c)9fst unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)? int retires (ef)f5f6f7f8fd
10024299192250002993619915100101010000101000050599821492678729951298673286811001020100002029951298671110021109101010000101000000640316332994810000102995229868299522986729952
10024299512240002993619915100101010000101000050599821492678729951298673285961001020100002029866299511110021109101010000101000020640216222986310000102995229867299522986829952
10024299512230002993619915100101010000101000050599821492678729951298663285971001020100002029865299511110021109101010000101000000640216232986410000102995229867299522986629952
10024299512240002993619915100101010000101000050599840492678429951298663285961001020100002029867299511110021109101010000101000000640316232986410000102986829952298682995229866
10024298652240002985219831100101010000101000050599821492687129866299513286811001020100002029951298671110021109101010000101000000640216222994810000102986829952298672995229868
10024298672240002985119829100101010000101000050599820492678529951298663285971001020100002029867299511110021109101010000101000000640316222994810000102995229867299522986729952
10024299512240002993619832100101010000101000050599821492687129867299513286811001020100002029951298671110021109101010000101000010640316332994810000102995229866299522986729952
10024299512241002985019831100101010000101000050599821492687129864299513286811001020100002029951298671110021109101010000101000000640216332986310000102986729952298672995229952
10024299512240002993619915100101010000101000050599821492678729951298673285961001020100002029866299511110021109101010000101000010640216332994810000102995229866299522986629952
10024299512230002985019832100101010000101000050599821492687129867299513286811001020100002029951298671110021109101010000101000000640216222994810000102986629952298672995229865