Firestorm: MSR (FPCR) measurements

Code:

  msr fpcr, x0

Initialization

  mrs x0, fpcr

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 0.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	3f	51	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	82	83	flush restart other nonspec (84)	85	inst all (8c)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	f5	f6	f7	f8	fd
1004	11028	85	0	0	11013	26	0	49	7948	11028	11028	10651	3	10756	11028	11028	1	1	1001	0	0	0	0	73	1	146	1	1	11025	11029	11029	11029	11029	11029
1004	11028	86	0	0	11013	26	0	49	7948	11028	11028	10651	3	10756	11028	11028	1	1	1001	0	0	1	0	73	1	146	1	1	11025	11029	11029	11029	11029	11029
1004	11028	86	0	0	11013	26	1	49	7948	11028	11028	10651	3	10756	11028	11028	1	1	1001	0	0	0	0	73	1	146	1	1	11025	11029	11029	11029	11029	11029
1004	11028	86	0	0	11013	26	0	49	7948	11028	11028	10651	3	10756	11028	11028	1	1	1001	0	0	0	0	73	1	146	1	1	11025	11029	11029	11029	11029	11029
1004	11028	85	0	0	11013	26	0	49	7948	11028	11028	10651	3	10756	11028	11028	1	1	1001	2	2	0	220	73	1	146	1	1	11025	11068	11029	11029	11029	11029
1004	11028	85	0	897	11013	26	0	49	7948	11028	11028	10651	3	10756	11028	11028	1	1	1001	0	0	0	3	73	1	146	1	1	11025	11029	11029	11029	11029	11029
1004	11028	85	0	0	11013	26	0	49	7948	11028	11028	10651	3	10756	11028	11028	1	1	1001	0	0	0	0	73	1	146	1	1	11025	11029	11029	11029	11029	11029
1004	11028	85	0	0	11013	26	1	49	7948	11028	11028	10651	3	10756	11028	11028	1	1	1001	0	0	0	0	73	1	146	1	1	11025	11029	11029	11029	11029	11029
1004	11028	85	0	0	11013	26	1	49	7948	11028	11028	10651	3	10756	11028	11028	1	1	1001	0	0	0	0	73	1	146	1	1	11025	11029	11029	11029	11029	11029
1004	11028	86	0	0	11013	26	0	49	7948	11028	11028	10651	3	10756	11028	11028	1	1	1001	0	0	0	0	73	1	146	1	1	11025	11029	11029	11029	11029	11029

Code:

  msr fpcr, x0

Initialization

  mrs x0, fpcr

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 11.0028

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int retires (ef)	f5	f6	f7	f8	fd
10204	110028	853	0	110013	26	100	100	100	500	0	49	106948	110028	110028	108617	7	108722	100	200	200	110028	87781	1	1	10201	100	99	100	100	100	0	0	0	1	1	1	719	24	0	0	110025	100	110029	110029	110029	110029	110029
10204	110028	853	12	110013	26	100	100	100	500	1	49	106948	110028	110028	108617	7	108722	100	200	200	110028	87781	1	1	10201	100	99	100	100	100	0	1	0	1	1	1	719	24	0	0	110025	100	110029	110029	110029	110029	110029
10204	110028	853	0	110013	26	100	100	100	500	0	49	106948	110028	110028	108617	7	108722	100	200	200	110028	87781	1	1	10201	100	99	100	100	100	0	0	0	1	1	1	719	24	0	0	110025	100	110029	110029	110029	110029	110029
10204	110028	853	12	110013	26	100	100	100	500	0	49	106948	110028	110028	108617	7	108722	100	200	200	110028	87781	1	1	10201	100	99	100	100	100	0	0	0	1	1	1	719	24	0	0	110025	100	110029	110029	110029	110029	110029
10204	110028	853	0	110013	26	100	100	100	500	0	49	106948	110028	110028	108617	7	108722	100	200	200	110028	87781	1	1	10201	100	99	100	100	100	0	1	0	1	1	1	719	24	3	0	110025	100	110029	110029	110029	110029	110067
10204	110028	853	12	110013	26	100	100	100	500	0	49	106948	110028	110028	108617	7	108722	100	200	200	110028	87781	1	1	10201	100	99	100	100	100	0	0	3	1	1	1	719	24	0	0	110025	100	110029	110029	110029	110029	110029
10204	110028	852	0	110013	26	100	100	100	500	0	49	106948	110028	110028	108617	7	108722	100	200	200	110028	87781	1	1	10201	100	99	100	100	100	0	1	0	1	1	1	719	24	0	0	110025	100	110029	110029	110029	110029	110029
10204	110028	853	0	110013	26	100	100	100	500	0	49	106948	110028	110028	108617	7	108722	100	200	200	110028	87781	1	1	10201	100	99	100	100	100	0	1	0	1	1	1	719	24	0	0	110025	100	110029	110029	110029	110029	110029
10204	110028	852	12	110013	26	100	100	100	500	0	49	106948	110028	110028	108617	7	108722	100	200	200	110028	87781	1	1	10201	100	99	100	100	100	0	0	3	1	1	1	719	24	0	0	110025	100	110029	110029	110029	110029	110029
10204	110028	853	0	110013	26	100	100	100	500	0	49	106948	110028	110028	108617	7	108722	100	200	200	110028	87781	1	1	10201	100	99	100	100	100	0	0	0	1	1	1	719	24	3	0	110025	100	110029	110029	110029	110029	110106

1000 unrolls and 10 iterations

Result (median cycles for code): 11.0028

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int retires (ef)	f5	f6	f7	f8	fd
10024	110028	853	0	0	0	0	0	0	0	0	0	110013	26	10	10	10	50	1	49	106948	110028	110028	108534	3	108639	10	20	20	110028	110028	1	1	10021	10	9	10	10	10	0	0	0	1	0	0	0	640	5	135	6	6	110025	10	110029	110029	110029	110029	110029
10024	110028	853	0	0	0	0	0	0	0	0	0	110013	26	10	10	10	50	0	49	106948	110028	110028	108534	3	108639	10	20	20	110028	110028	1	1	10021	10	9	10	10	10	0	0	0	0	0	0	0	640	6	135	6	6	110025	10	110029	110029	110029	110029	110029
10024	110028	853	0	0	0	0	0	0	0	0	0	110013	26	10	10	10	50	1	49	106948	110028	110028	108534	3	108639	10	20	20	110028	110028	1	1	10021	10	9	10	10	10	0	0	0	0	0	3	0	640	6	135	6	6	110025	10	110029	110029	110029	110031	110029
10024	110028	853	0	0	0	0	0	0	0	0	0	110013	26	10	10	10	50	1	49	106948	110028	110028	108585	3	108639	10	20	20	110028	110028	1	1	10021	10	9	10	10	10	0	0	0	0	0	0	0	640	7	135	7	7	110025	10	110029	110029	110029	110029	110029
10024	110028	852	0	0	0	0	0	0	0	0	0	110013	26	10	10	10	50	1	49	106948	110028	110028	108534	3	108639	10	20	20	110028	110028	1	1	10021	10	9	10	10	10	0	0	0	2	2	821	0	640	7	135	7	7	110025	10	110029	110029	110029	110029	110029
10024	110028	853	0	0	0	0	0	0	0	0	0	110013	26	10	10	10	50	1	49	106948	110028	110029	108534	3	108639	10	20	20	110028	110028	1	1	10021	10	9	10	10	10	0	0	0	1	0	3	0	640	7	167	11	7	110025	10	110029	110029	110029	110029	110029
10024	110028	853	0	0	0	0	0	0	0	0	0	110013	26	10	10	10	50	1	49	106948	110028	110028	108534	3	108639	10	20	20	110028	110028	1	1	10021	10	9	10	10	10	0	0	0	1	0	0	0	640	5	135	7	7	110025	10	110029	110029	110029	110029	110029
10024	110028	853	0	0	0	0	0	0	0	0	0	110013	26	10	10	10	50	1	49	106948	110028	110028	108534	3	108639	10	20	20	110028	110028	1	1	10021	10	9	10	10	10	0	0	0	0	0	0	0	640	6	135	6	6	110025	10	110029	110029	110029	110029	110029
10024	110028	852	0	0	0	0	0	0	0	0	0	110013	26	10	10	10	50	1	49	106948	110028	110028	108534	3	108639	10	20	20	110028	110028	1	1	10021	10	9	10	10	10	0	0	0	0	0	0	0	640	7	135	7	7	110025	10	110029	110029	110029	110029	110029
10024	110028	853	0	0	0	0	0	0	0	0	0	110013	26	10	10	10	50	1	49	106948	110028	110028	108534	3	108639	10	20	20	110028	110028	1	1	10021	10	9	10	10	10	0	0	0	0	0	0	0	640	6	135	6	6	110025	10	110029	110029	110029	110029	110029

MSR (FPCR)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations