Firestorm: AUTDZB measurements

Code:

  autdzb x0

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	7029	70	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	0	73	2	85	2	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	12	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	0	73	1	85	1	1	6852	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	1	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	71	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	71	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	1	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	0	272	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	3	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	0	61	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	0	103	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	0	105	5824	25	1000	1000	1000	178330	0	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	1	3	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030
1004	7029	70	0	61	5824	25	1000	1000	1000	178330	1	49	3949	7029	7029	6623	3	6818	1000	1000	1000	7029	870	1	1	1001	1000	0	0	0	73	1	85	1	1	6789	1000	1000	7030	7030	7030	7030	7030

Test 2: Latency 1->1

Code:

  autdzb x0

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	ec	? int retires (ef)	f5	f6	f7	f8	fd
10204	70029	675	0	0	0	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	710	1	79	1	1	69796	10100	72	0	10100	70030	70030	70030	70030	70030
10204	70029	680	0	0	0	0	631	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	710	1	79	1	1	69796	10100	0	0	10100	70030	70030	70030	70030	70030
10204	70029	691	0	0	0	0	103	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	710	1	79	1	1	69796	10100	0	0	10100	70030	70030	70030	70030	70030
10204	70029	679	0	0	0	0	103	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	65	0	0	710	1	79	1	1	69796	10100	0	0	10100	70030	70030	70030	70030	70030
10204	70029	679	0	0	0	0	726	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	710	2	79	1	1	69796	10100	0	0	10100	70030	70030	70030	70030	70030
10204	70029	686	0	0	0	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	710	1	79	1	1	69796	10100	0	0	10100	70030	70030	70055	70030	70030
10204	70029	679	0	0	0	0	346	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	710	1	79	1	1	69796	10100	0	0	10100	70030	70030	70030	70030	70030
10204	70029	686	0	0	0	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	710	1	79	1	1	69796	10100	0	0	10100	70030	70030	70030	70030	70030
10204	70029	674	0	0	0	0	105	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	710	1	79	1	1	69796	10100	0	0	10100	70030	70030	70030	70030	70030
10204	70029	679	0	0	0	0	61	59824	25	10200	10200	10200	1808330	0	49	66949	0	70029	70029	68480	3	68674	10200	10200	10200	70029	912	1	1	10201	100	99	10100	0	0	0	710	1	79	1	1	69796	10100	0	0	10100	70030	70030	70030	70030	70030

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0029

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	70029	614	0	0	1	0	0	12	0	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	619	0	0	0	0	0	0	0	0	404	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	1	0	0	640	7	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	619	0	0	0	0	0	12	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	1	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	619	0	0	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	70069	70029	68502	3	68696	10020	10080	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	6	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	620	0	0	0	0	0	0	0	0	253	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	619	0	0	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70068	870	2	1	10021	10	9	10010	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	624	0	0	0	0	0	0	0	0	117	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	622	0	0	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	618	0	0	0	0	0	0	0	0	89	59824	25	10020	10020	10020	1807430	1	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	2	79	2	2	69805	10010	10010	70030	70030	70030	70030	70030
10024	70029	622	0	0	0	0	0	0	0	0	61	59824	25	10020	10020	10020	1807430	0	49	66949	70029	70029	68502	3	68696	10020	10020	10020	70029	870	1	1	10021	10	9	10010	0	0	0	0	0	640	2	79	3	2	69805	10010	10010	70030	70030	70030	70030	70030

Test 3: throughput

Count: 8

Code:

  autdzb x0
  autdzb x1
  autdzb x2
  autdzb x3
  autdzb x4
  autdzb x5
  autdzb x6
  autdzb x7

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? int retires (ef)	f5	f6	f7	f8	fd
80204	80040	643	0	0	0	0	12	0	70	28	80205	80205	80207	401030	1	49	76960	0	80040	80041	69980	7	69990	80207	80224	80224	80041	164	1	1	80201	100	99	80100	0	0	1	0	3	0	0	0	5110	2	25	2	2	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	645	0	0	0	0	12	0	77	25	80200	80200	80200	401000	1	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	1	0	3	0	0	0	5110	2	25	2	2	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	645	0	0	0	0	12	0	628	25	80200	80200	80200	401000	1	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	7	0	3	0	0	0	5110	2	25	2	2	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	646	0	0	0	0	12	0	35	25	80200	80200	80200	401000	0	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	701	0	0	0	0	0	0	77	25	80200	80200	80200	401000	0	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	699	0	0	0	0	0	0	1130	25	80200	80200	80200	401000	1	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	12	0	77	25	80200	80200	80200	401000	0	49	76955	3	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	5110	2	25	4	2	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	27	0	1000	25	80200	80200	80200	401000	1	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	1	0	0	0	0	0	5110	2	25	2	2	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	703	0	0	0	0	0	0	35	25	80200	80200	80200	401000	1	49	76955	0	80035	80035	69966	3	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	0	80100	80036	80036	80036	80036	80036
80204	80035	702	0	0	0	0	0	0	35	25	80200	80200	80200	401000	0	49	76955	0	80035	80035	69966	19	69984	80200	80200	80200	80035	164	1	1	80201	100	99	80100	0	0	0	0	0	0	0	0	5110	2	25	2	2	80025	80100	0	80100	80036	80036	80036	80036	80036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	61	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	9e	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? int retires (ef)	f5	f6	f7	f8	fd
80024	80035	695	0	0	0	0	0	0	0	0	0	705	25	80020	80020	80020	400100	0	0	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	0	0	5020	2	3	25	2	2	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	702	0	0	0	0	0	0	0	0	0	35	25	80020	80020	80020	400100	1	2	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	3	0	0	5020	2	3	25	2	2	80027	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	702	0	0	0	0	0	0	0	12	0	91	25	80020	80020	80020	400100	0	0	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	0	0	5020	0	3	25	2	3	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	702	0	0	0	0	0	0	0	0	0	700	25	80020	80020	80020	400100	1	2	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	0	0	5020	0	2	25	2	2	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	701	0	0	0	0	0	0	0	0	0	35	25	80020	80020	80020	400100	0	2	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	0	0	5020	0	3	25	2	2	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	702	0	0	0	0	0	0	0	12	0	105	25	80020	80020	80020	400100	0	2	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	0	0	5020	2	3	25	3	3	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	701	0	0	0	0	0	0	0	0	0	35	25	80020	80020	80020	400100	0	2	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	3	0	0	5020	2	2	25	2	2	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	702	0	0	0	0	0	0	0	0	0	35	25	80020	80020	80020	400100	0	2	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	0	0	5020	2	2	25	3	3	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	702	0	0	0	0	0	0	0	0	0	35	25	80020	80020	80020	400100	1	2	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	0	0	5020	2	3	25	3	2	80024	80010	0	80010	80036	80036	80036	80036	80036
80024	80035	702	0	0	0	0	0	0	0	0	0	35	25	80020	80020	80020	400100	0	0	49	76955	80035	80035	69988	3	70006	80020	80020	80020	80035	164	1	1	80021	10	9	80010	0	0	0	0	0	0	0	0	0	0	5020	2	2	25	3	3	80024	80037	0	80010	80036	80036	80036	80036	80036

AUTDZB

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations