Firestorm: LDRSW (register, lsl) measurements

Code:

  ldrsw x0, [x6, x7, lsl #2]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	394	3	1	0	0	45	0	0	1	379	2	12	12	16	25	1000	1000	1000	15037	0	394	374	217	3	252	1000	1000	2000	394	77	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	6	1	39	43	73	2	16	2	2	371	0	10	4	1000	395	395	395	395	395
1004	374	2	0	0	0	0	1	0	1	379	0	0	12	16	25	1000	1000	1000	15037	1	374	394	217	3	252	1000	1000	2000	394	56	1	1	1001	1000	1000	0	1000	0	1000	0	39	1039	6	1	39	43	73	2	16	2	2	391	0	0	0	1000	395	395	395	375	395
1004	394	3	0	0	0	45	1	0	0	379	0	0	0	0	25	1000	1000	1000	15037	1	394	394	197	3	253	1000	1000	2000	394	56	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	0	0	39	0	73	2	16	2	2	371	10	0	4	1000	375	395	395	395	395
1004	394	3	1	1	0	45	1	0	1	379	3	12	12	16	25	1000	1000	1000	14989	0	394	394	217	3	252	1000	1000	2000	374	77	1	1	1001	1000	1000	0	1000	43	1039	0	0	1039	6	1	39	0	73	2	16	2	2	391	0	10	4	1000	395	396	395	395	395
1004	394	3	0	0	0	45	1	0	1	379	2	12	12	16	25	1000	1000	1000	15037	1	374	374	217	3	232	1000	1000	2000	394	56	1	1	1001	1000	1000	0	1000	43	1039	0	0	1000	6	1	39	43	73	2	16	2	2	391	10	10	0	1000	395	395	375	395	375
1004	374	3	0	0	0	0	0	0	1	379	2	12	12	16	25	1000	1000	1000	14989	1	394	394	217	3	232	1000	1000	2000	394	77	1	1	1001	1000	1000	0	1000	43	1000	0	39	1039	6	1	0	43	73	2	16	2	2	391	0	10	4	1000	395	398	395	375	395
1004	394	3	0	0	0	45	0	0	0	379	2	12	12	16	25	1000	1000	1000	15018	1	394	394	216	3	252	1000	1000	2000	394	77	1	1	1001	1000	1000	1	1000	43	1039	0	39	1039	6	1	39	43	73	2	16	2	2	391	10	10	0	1000	395	375	395	395	395
1004	394	3	0	0	0	45	1	0	1	379	2	12	12	16	25	1000	1000	1000	14989	1	394	394	217	3	252	1000	1000	2000	374	77	1	1	1001	1000	1000	0	1000	43	1000	0	39	1039	6	1	39	43	73	2	16	2	2	394	10	10	4	1000	395	395	395	375	375
1004	394	2	0	1	1	45	1	0	0	359	2	12	12	0	25	1000	1000	1000	14989	1	394	394	217	3	252	1000	1000	2000	394	77	1	1	1001	1000	1000	0	1000	43	1039	0	39	1039	0	1	0	43	73	2	16	2	2	391	10	10	4	1000	395	395	395	395	395
1004	394	3	0	0	0	45	0	0	1	359	2	0	12	0	25	1000	1000	1000	15037	1	394	394	217	3	232	1000	1000	2000	374	77	1	1	1001	1000	1000	0	1000	43	1000	0	0	1000	6	1	39	43	73	2	16	2	2	391	0	10	4	1000	395	395	395	375	397

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsw x0, [x6, x7, lsl #2]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0053

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70047	524	0	0	0	0	0	0	0	0	2	1	0	0	70032	69759	59706	25	40104	30103	10002	30100	10000	616015	3342062	1	49	66967	70047	70047	64646	3	64950	40100	30200	10054	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	1	0	0	10000	1	0	1	0	0	2610	1	71	1	1	69810	30003	6	6	6	10000	30100	70049	70048	70048	70048	70048
40204	70047	525	0	0	0	0	0	0	0	0	1	1	0	0	70032	69735	59706	25	40104	30103	10001	30100	10000	616015	3342062	1	49	66967	70047	70047	64643	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	0	10000	0	0	0	10000	1	0	1	0	0	2610	1	71	1	1	69810	30003	6	6	6	10000	30100	70050	70048	70048	70036	70048
40204	70047	525	0	0	0	0	0	0	0	0	1	1	0	0	70032	69735	59706	25	40104	30100	10001	30100	10000	616015	3342062	1	49	66967	70047	70047	64643	3	64950	40100	30200	10000	60200	20000	70035	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	2610	1	71	1	1	69816	30006	6	6	6	10000	30100	70054	70054	70054	70054	70054
40204	70053	525	1	0	0	0	0	0	0	0	2	1	0	1	70038	69784	59712	25	40108	30106	10002	30100	10000	616032	3341769	1	49	66973	70053	70053	64649	3	64956	40100	30200	10000	60200	20000	70053	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10003	1	1	10001	0	1	31	10000	1	1	1	1	0	2610	1	71	1	1	69816	30006	6	6	6	10000	30100	70059	70061	70054	70054	70054
40204	70053	524	1	0	0	1	0	0	0	0	2	0	0	1	70038	69784	59712	25	40108	30106	10002	30100	10000	616032	3342350	1	49	66961	70053	70053	64649	3	64956	40100	30200	10000	60200	20000	70053	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10001	2	1	10002	0	1	1	10000	1	1	1	1	2	2610	1	71	1	1	69816	30006	6	6	6	10000	30100	70059	70054	70057	70054	70054
40204	70053	524	1	1	1	1	0	0	0	0	2	1	0	1	70038	69790	59707	25	40104	30103	10001	30100	10000	616015	3342062	1	49	66967	70047	70047	64643	3	64950	40100	30200	10000	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10000	0	1	10000	0	0	0	10000	1	0	1	0	0	2610	1	71	1	1	69810	30003	6	0	6	10000	30100	70061	70056	70054	70054	70112
40204	70054	525	1	0	1	1	0	0	0	0	2	1	0	1	70038	69784	59712	25	40108	30106	10002	30100	10000	616032	3342350	1	49	66973	70053	70053	64637	3	64956	40100	30200	10000	60200	20000	70053	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10002	2	1	10001	0	0	1	10000	1	1	1	1	1	2610	1	71	1	1	69816	30006	6	6	6	10000	30100	70058	70059	70054	70054	70054
40204	70053	525	1	0	1	0	0	0	0	0	2	0	0	1	70038	69784	59701	25	40104	30106	10002	30100	10000	616032	3342350	1	49	66973	70053	70041	64649	3	64956	40100	30200	10000	60200	20132	70053	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10002	2	1	10002	0	0	1	10000	1	1	1	1	2	2610	1	71	1	1	69816	30006	6	6	6	10000	30100	70065	70055	70054	70054	70054
40204	70053	524	1	1	1	1	0	0	0	0	2	1	0	1	70038	69786	59712	25	40108	30106	10002	30100	10000	616032	3342350	0	49	66973	70047	70047	64643	3	64950	40100	30200	10067	60200	20000	70047	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10002	2	1	10001	0	0	1	10000	1	1	1	1	0	2610	1	71	1	1	69816	30006	6	6	6	10000	30100	70086	70111	70055	70042	70054
40204	70053	525	1	1	1	1	1	0	0	0	2	1	0	1	70038	69784	59712	25	40108	30106	10002	30100	10000	616032	3342350	1	49	66973	70053	70053	64649	3	64956	40100	30200	10000	60200	20000	70053	35	1	1	40201	100	99	100	10000	30100	10000	1	100	10002	2	1	10002	0	2	1	10000	1	1	1	1	1	2610	1	71	1	1	69816	30006	6	6	6	10000	30100	70055	70055	70055	70054	70054

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0054

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	0e	0f	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70051	525	1	1	0	0	127	0	0	3	70036	69775	59713	25	40014	30013	10001	30010	10000	617068	3342254	49	66974	70054	70051	64748	3	64960	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	10000	1	1	2526	14	71	14	14	69798	30000	0	0	13	10000	30010	70055	70055	70055	70036	70055
40024	70051	525	1	1	0	0	1	0	0	3	70020	69743	59695	25	40010	30013	10001	30010	10000	617018	3341470	49	66974	70035	70054	64759	3	64979	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	1	10000	0	0	10000	0	1	2526	16	71	17	17	69817	30003	13	0	0	10000	30010	70055	70055	70036	70036	70052
40024	70035	525	1	1	0	0	1	0	0	3	70039	69778	59713	25	40014	30013	10001	30010	10000	617018	3342398	49	66974	70054	70035	64793	3	64960	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	1	0	10000	1	0	2526	17	71	14	17	69814	30000	13	13	0	10000	30010	70052	70055	70055	70052	70055
40024	70054	524	1	1	0	0	82	1	0	3	70039	69775	59695	25	40010	30013	10001	30010	10000	617018	3342398	49	66974	70054	70054	64767	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	10000	1	1	2526	16	71	16	16	69817	30003	0	13	10	10000	30010	70055	70055	70036	70036	70036
40024	70035	524	1	1	0	0	21	1	0	3	70039	69778	59713	25	40014	30010	10000	30010	10000	617018	3342398	49	66974	70056	70054	64758	3	64979	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10000	0	1	10000	0	0	10000	1	1	2526	19	71	15	8	69817	30003	0	10	0	10000	30010	70036	70055	70055	70052	70055
40024	70054	525	1	1	0	0	55	1	0	3	70039	69743	59695	25	40014	30013	10000	30010	10000	617068	3341470	49	66955	70054	70054	64750	3	64981	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	10000	1	1	2526	9	71	13	15	69814	30000	13	13	10	10000	30010	70055	70036	70052	70052	70055
40024	70035	525	1	1	0	0	25	1	0	3	70039	69743	59713	25	40010	30013	10000	30010	10000	616991	3342254	49	66955	70054	70054	64755	3	64960	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	10000	1	0	2526	13	71	15	15	69814	30000	13	13	0	10000	30010	70036	70055	70055	70052	70055
40024	70051	525	1	1	0	0	52	1	0	3	70020	69775	59695	25	40014	30013	10001	30010	10000	617018	3342254	49	66971	70035	70051	64784	3	64960	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	10000	1	1	2526	16	71	14	16	69814	30000	0	13	13	10000	30010	70055	70036	70059	70055	70055
40024	70054	525	1	1	0	0	1	0	0	3	70039	69778	59713	25	40014	30010	10001	30010	10000	617018	3342398	49	66974	70054	70054	64754	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	1	10000	0	0	10000	1	1	2526	11	71	10	17	69798	30003	13	10	10	10000	30010	70036	70055	70036	70036	70055
40024	70054	524	1	1	0	0	1	1	0	3	70039	69775	59695	25	40014	30010	10000	30010	10000	617018	3342398	49	66974	70056	70035	64752	3	64960	40010	30020	10000	60020	20000	70054	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	0	0	10000	0	0	10000	0	0	2526	9	71	15	13	69817	30003	0	0	13	10000	30010	70055	70055	70055	70052	70055

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsw x0, [x6, x7, lsl #2]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40205	70057	524	1	0	1	1	1	1	1	0	1	70042	69782	59710	25	40104	30103	10002	30100	10000	616014	3342254	1	49	66971	70051	70051	64647	0	3	64960	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	1	10001	0	0	1	1	10000	1	0	1	0	0	2610	1	71	1	1	69820	30006	10	10	10	10000	30100	70052	70052	70052	70052	70052
40204	70051	525	0	0	0	0	0	1	1	0	0	70145	69788	59716	25	40108	30106	10002	30100	10000	616068	3342542	1	49	66977	70057	70057	64653	0	3	64960	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	3	0	0	10000	1	0	1	0	0	2610	1	71	1	1	69814	30006	10	10	10	10000	30100	70052	70052	70052	70052	70052
40204	70051	524	0	0	0	0	0	1	1	0	0	70042	69782	59710	25	40100	30103	10001	30100	10000	616014	3342254	0	49	66971	70051	70088	64647	0	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	0	2610	1	71	1	1	69814	30006	10	10	10	10000	30100	70052	70052	70052	70052	70052
40204	70052	525	0	0	0	0	0	1	1	0	0	70042	69782	59710	25	40104	30103	10001	30100	10000	616175	3342254	1	49	66971	70051	70051	64647	0	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10003	1	1	10003	0	0	2	4	10000	1	1	1	1	1	2610	1	71	1	1	69820	30006	10	10	10	10000	30100	70052	70052	70052	70052	70052
40204	70051	524	0	0	0	1	0	1	1	0	0	70042	69788	59716	25	40108	30106	10002	30100	10000	616068	3341769	1	49	66961	70057	70057	64653	0	3	64960	40100	30200	10000	60200	20000	70041	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	1	0	3	10000	1	1	1	1	1	2610	1	71	1	1	69820	30006	10	10	10	10000	30100	70052	70052	70052	70052	70052
40204	70051	524	0	0	0	0	0	1	1	0	0	70042	69782	59710	25	40104	30103	10001	30100	10000	616014	3342254	1	49	66971	70051	70051	64647	0	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	3	1	10006	0	0	2	1	10000	1	1	1	1	0	2610	1	71	1	1	69827	30006	10	10	10	10000	30100	70052	70052	70053	70052	70052
40204	70051	524	0	0	0	0	0	1	1	0	0	70042	69788	59716	25	40108	30106	10002	30100	10000	616068	3342542	1	49	66977	70057	70057	64653	0	3	64960	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	0	2610	1	71	1	1	69814	30018	10	10	10	10000	30100	70052	70052	70052	70052	70052
40204	70051	526	0	0	0	0	0	1	1	0	0	70042	69788	59716	25	40108	30106	10002	30100	10000	616068	3342542	1	49	66977	70057	70057	64653	0	3	64944	40100	30200	10000	60200	20000	70057	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10000	0	1	10000	0	0	0	0	10000	1	0	1	0	0	2610	1	71	1	1	69814	30006	10	10	10	10000	30100	70058	70058	70058	70058	70045
40204	70057	524	1	1	1	0	0	2	1	0	1	70042	69764	59710	25	40104	30103	10000	30100	10000	616014	3342254	1	49	66971	70051	70051	64647	0	3	64954	40100	30200	10000	60200	20000	70051	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10001	2	1	10002	0	0	0	1	10000	1	1	1	1	1	2610	1	71	1	1	69901	30006	10	10	10	10000	30100	70052	70052	70052	70052	70052
40204	70051	524	0	0	0	1	0	1	1	0	0	70042	69788	59716	25	40108	30106	10002	30100	10000	616068	3342542	1	49	66977	70057	70057	64653	0	3	64960	40100	30200	10000	60200	20000	70057	79	1	1	40201	100	99	100	10000	30100	10000	0	100	10002	1	1	10002	0	0	0	1	10000	1	1	1	1	0	2610	1	71	1	1	69820	30006	10	10	10	10000	30100	70052	70052	70136	70057	70052

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0051

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	1e	22	23	3f	4d	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	l1d cache miss ld nonspec (bf)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
40025	70051	525	0	0	0	0	0	0	0	139	1	0	70036	69775	59710	25	40014	30013	10002	30010	10000	616991	3342254	0	0	49	66971	70051	70051	64748	3	64982	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	2520	1	71	2	1	69820	30006	10	10	0	10000	30010	70058	70058	70058	70058	70058
40024	70057	525	1	0	1	1	0	0	0	57	1	0	70036	69775	59710	25	40014	30013	10001	30010	10000	616991	3342254	0	0	49	66971	70051	70035	64764	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	0	1	0	0	2520	1	71	1	1	69820	30003	0	10	10	10000	30010	70052	70052	70052	70052	70052
40024	70051	524	0	0	0	0	0	0	0	73	1	0	70036	69775	59710	25	40014	30010	10001	30010	10000	616991	3342254	0	0	49	66971	70051	70051	64669	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	2520	1	71	3	2	69804	30006	10	10	10	10000	30010	70052	70052	70052	70052	70052
40024	70051	524	0	0	0	0	0	0	0	52	1	0	70036	69775	59710	25	40014	30013	10001	30010	10000	616991	3342254	0	0	49	66971	70051	70051	64781	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	0	0	0	2520	3	71	2	2	69820	30006	10	10	10	10000	30010	70052	70036	70052	70089	70036
40024	70051	524	0	0	0	0	0	0	0	61	1	0	70036	69775	59710	25	40014	30013	10001	30010	10000	616991	3342254	0	0	49	66971	70051	70051	64756	3	64976	40010	30020	10000	60020	20000	70035	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	2520	1	71	1	1	69804	30006	10	10	10	10000	30010	70058	70058	70052	70052	70269
40024	70051	525	0	0	0	0	0	0	0	1	1	0	70036	69775	59710	25	40014	30013	10001	30010	10000	616991	3342254	0	0	49	66971	70051	70051	64728	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	2520	4	71	1	1	69820	30003	10	10	0	10000	30010	70058	70058	70052	70052	70052
40024	70051	524	0	0	0	0	0	0	0	34	1	0	70036	69775	59695	25	40014	30013	10001	30010	10000	616991	3342254	0	0	49	66971	70051	70051	64759	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	3	10000	1	0	0	0	2520	2	71	1	2	69820	30003	10	0	10	10000	30010	70058	70058	70052	70052	70052
40024	70051	525	0	0	0	0	0	1	0	25	1	0	70036	69775	59710	25	40014	30013	10001	30010	10000	616991	3342254	0	0	49	66971	70057	70078	64717	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	0	0	10000	1	1	0	0	2520	1	71	1	1	69820	30006	10	0	10	10000	30010	70059	70058	70052	70037	70052
40024	70163	524	0	0	0	0	0	0	0	0	1	0	70036	69775	59695	25	40014	30013	10001	30010	10000	616991	3342254	0	0	49	66955	70051	70051	64739	3	64976	40010	30020	10000	60410	20000	70089	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10000	1	10000	50	0	10000	1	1	0	1	2520	1	71	2	2	69820	30006	10	10	10	10000	30010	70058	70052	70052	70052	70052
40024	70051	524	0	0	0	0	1	0	0	0	1	0	70036	69775	59710	25	40014	30013	10001	30010	10000	616991	3341470	0	0	49	66971	70051	70134	64670	3	64976	40010	30020	10000	60020	20000	70051	35	1	1	40022	10	9	10	10000	30010	10000	0	10	10000	1	10000	1	0	10000	1	1	0	0	2520	2	71	2	1	69820	30006	10	10	10	10000	30010	70052	70036	70052	70036	70036

Test 4: throughput

Count: 8

Code:

  ldrsw x0, [x6, x7, lsl #2]
  ldrsw x0, [x6, x7, lsl #2]
  ldrsw x0, [x6, x7, lsl #2]
  ldrsw x0, [x6, x7, lsl #2]
  ldrsw x0, [x6, x7, lsl #2]
  ldrsw x0, [x6, x7, lsl #2]
  ldrsw x0, [x6, x7, lsl #2]
  ldrsw x0, [x6, x7, lsl #2]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	22	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	26734	200	1	0	1	1	0	0	0	0	65	0	1	3	26718	2	18	18	17	25	80100	100	80000	100	80015	500	1159239	1	49	23653	26734	26714	16642	6	16684	80116	200	80024	200	160048	26734	83	1	1	80201	100	99	100	80000	100	80000	0	100	80020	20	42	0	80060	0	0	0	66	80041	3	1	60	42	19	0	1	1	1	5118	0	16	0	0	26746	10	10	3	80000	100	26734	26735	26734	26734	26735
80204	26734	200	1	1	0	0	0	0	0	0	21	0	1	2	26718	3	18	18	17	25	80100	100	80000	100	80015	500	1167811	0	49	24109	26734	26733	16661	6	16685	80116	200	80024	200	160048	26733	82	1	1	80201	100	99	100	80000	100	80000	0	100	80019	20	42	0	80060	1	0	1	62	80041	3	1	60	0	19	3	1	1	1	5118	0	16	0	0	26730	10	10	3	80000	100	26734	26734	26734	26734	26734
80204	26733	200	1	0	0	1	0	0	0	0	65	0	1	3	26719	2	18	18	16	25	80100	100	80000	100	80016	500	1167617	0	49	23654	26734	26733	16661	6	16685	80117	200	80024	200	160048	26733	82	1	1	80201	100	99	100	80000	100	80000	0	100	80021	20	42	0	80060	1	0	1	62	80041	3	1	61	0	19	1	1	1	1	5118	0	16	0	0	26730	10	10	3	80000	100	26735	26734	26734	26734	26734
80204	26733	200	1	1	0	0	0	0	0	0	64	0	1	2	26723	0	18	18	16	25	80100	100	80000	100	80016	500	1167559	0	49	23653	26714	26733	16661	6	16685	80116	200	80024	200	160048	26733	82	1	1	80201	100	99	100	80000	100	80000	0	100	80415	21	42	96	80197	1	0	1	62	80042	3	1	60	42	19	0	1	1	1	5118	0	16	0	0	26733	10	10	3	80000	100	26734	26734	26734	26734	26735
80204	26714	200	1	0	0	0	0	0	0	0	65	0	1	2	26718	2	18	18	206	25	80100	100	80000	100	80016	500	1169805	1	49	23654	26733	26733	16661	6	16686	80116	200	80024	200	160048	26733	83	1	1	80201	100	99	100	80000	100	80000	0	100	80019	19	42	0	80060	0	0	2	62	80041	3	1	60	42	19	1	1	1	1	5117	0	16	0	0	26730	10	10	3	80000	100	26734	26734	26734	26735	26734
80204	26733	200	1	0	0	1	0	0	0	0	65	0	1	3	26718	3	18	0	17	25	80100	100	80000	100	80016	500	1167811	1	49	23653	26733	26735	16660	6	16684	80116	200	80024	200	160048	26734	82	1	1	80201	100	99	100	80000	100	80000	0	100	80020	19	42	0	80060	1	0	1	62	80041	3	1	60	42	19	0	1	1	1	5118	0	16	0	0	26736	10	10	3	80000	100	26734	26738	26734	26734	26734
80204	26733	201	1	1	0	1	0	0	0	0	65	0	1	2	26725	2	18	18	0	25	80100	100	80000	100	80016	500	1169611	0	49	23653	26734	26733	16661	6	16755	80116	200	80024	200	160048	26733	82	1	1	80201	100	99	100	80000	100	80000	0	100	80021	20	42	0	80060	1	0	1	61	80041	3	1	61	42	19	2	2	2	2	5128	1	23	1	1	26730	10	10	3	80000	100	26738	26734	26766	26734	26738
80204	26733	200	1	0	0	1	0	0	0	0	65	0	1	3	26718	2	18	0	0	25	80100	100	80000	100	80019	500	1166770	1	49	23635	26733	26733	16636	30	16672	80122	200	80030	200	160060	26733	82	1	1	80201	100	99	100	80000	100	80000	0	100	80020	19	42	0	80061	0	0	1	62	80041	3	0	60	42	18	0	2	2	2	5128	1	23	1	1	26736	10	10	3	80000	100	26734	26735	26734	26734	26734
80204	26733	200	1	1	0	0	1	0	0	0	65	0	1	3	26718	2	18	18	18	25	80100	100	80000	100	80020	500	1167102	1	49	23653	26733	26733	16651	9	16673	80121	200	80030	200	160060	26733	82	1	1	80201	100	99	100	80000	100	80000	0	100	80020	20	42	0	80062	1	0	1	65	80043	3	1	60	42	19	2	2	2	2	5128	1	23	1	1	26712	10	10	3	80000	100	26734	26734	26734	26734	26734
80204	26733	200	1	1	0	1	0	0	0	0	65	0	1	3	26718	2	21	18	16	25	80100	100	80000	100	80021	500	1167322	1	49	23653	26733	26733	16651	10	16673	80121	200	80030	200	160060	26734	83	1	1	80201	100	99	100	80000	100	80000	1	100	80020	19	42	0	80060	1	0	1	62	80041	3	0	60	42	19	1	2	2	2	5128	1	23	1	1	26735	10	10	3	80000	100	26734	26734	26734	26734	26734

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	0f	1e	22	23	3a	3f	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	a5	ld unit uop (a6)	l1d cache writeback (a8)	ac	af	b5	b6	bb	l1d cache miss ld nonspec (bf)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	26728	200	0	0	0	0	0	44	1	0	1	26714	0	0	12	17	25	80010	10	80000	10	80534	50	1171382	1	1	49	23628	26729	26729	16652	3	16709	80010	20	80000	20	160000	26708	78	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	43	0	80042	1	54	80042	3	1	42	43	2	1	5020	21	16	13	13	26725	11	11	4	80000	10	26709	26730	26730	26730	26791
80024	26712	200	0	0	0	1	1	0	0	0	1	26693	2	12	12	140	25	80010	10	80000	10	80000	50	1168891	0	1	49	23648	26729	26728	16652	3	16709	80010	20	80000	20	160000	26708	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80042	0	42	80000	0	0	42	0	0	0	5020	18	16	10	13	26725	11	0	4	80000	10	26730	26709	26730	26709	26710
80024	26708	200	0	0	0	0	0	0	0	0	1	26713	0	12	0	119	25	80010	10	80000	10	80000	50	1166750	0	1	49	23648	26732	26732	16673	3	16709	80010	20	80000	20	160000	26729	78	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80042	0	0	80042	0	1	0	0	0	0	5020	18	16	10	13	26705	11	0	4	80000	10	26729	26729	26729	26729	26869
80024	26729	200	0	0	0	0	0	45	1	0	0	26714	2	12	12	111	25	80010	10	80000	10	80000	50	1166750	0	1	49	23628	26728	26728	16673	3	16688	80010	20	80000	20	160000	26728	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	43	0	80042	6	48	80042	3	1	0	43	0	0	5020	13	16	12	8	26705	11	11	4	80000	10	26730	26709	26730	26709	26732
80024	26734	200	0	0	0	0	0	45	1	0	0	26693	2	12	12	17	25	80010	10	80000	10	80000	50	1168891	0	1	49	23649	26728	26708	16652	3	16708	80010	20	80000	20	160000	26732	78	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	43	0	80042	0	60	80042	3	0	0	43	0	0	5020	11	16	18	13	26705	0	11	4	80000	10	26730	26730	26730	26729	26711
80024	26714	200	0	0	0	0	0	0	1	0	1	26713	0	0	12	17	25	80010	10	80520	10	80000	50	1168285	0	0	49	23648	26729	26728	16652	3	16709	80010	20	80000	20	160000	26729	78	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80042	0	3	80042	3	1	42	0	0	0	5020	13	16	18	17	26726	0	11	0	80000	10	26709	26709	26729	26729	26711
80024	26733	200	0	0	0	0	1	45	1	0	1	26713	2	12	12	0	25	80010	10	80000	10	80000	50	1166934	0	1	49	23648	26728	26728	16673	3	16688	80010	20	80000	20	160000	26708	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80000	1	9	80042	0	1	42	0	0	0	5020	10	16	13	10	26726	0	11	0	80000	10	26730	26709	26709	26730	26714
80024	26745	200	0	0	0	0	0	0	0	0	1	26716	2	12	12	17	25	80010	10	80000	10	80000	50	1168891	0	1	49	23649	26729	26708	16673	3	16688	80010	20	80000	20	160000	26729	56	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	0	0	80042	0	57	80042	3	0	42	43	0	0	5020	17	16	13	13	26725	11	11	0	80000	10	26730	26709	26730	26730	26737
80024	26741	201	0	0	0	0	0	45	1	0	0	26714	2	0	0	17	25	80010	10	80000	10	80000	50	1168891	0	1	49	23649	26729	26728	16652	3	16688	80010	20	80000	20	160000	26729	78	1	1	80021	10	9	10	80000	10	80000	0	10	80000	0	43	0	80042	1	51	80042	3	0	42	0	0	0	5020	13	16	10	13	26705	11	11	0	80000	10	26730	26730	26709	26709	26730
80024	26725	200	0	0	0	0	0	0	1	0	1	26713	2	12	0	201	25	80010	10	80000	10	80000	50	1168891	0	1	49	23628	26728	26708	16652	3	16709	80010	20	80000	20	160000	26708	78	1	1	80021	10	9	10	80000	10	80000	1	10	80000	0	43	0	80042	0	12	80000	0	1	42	43	0	0	5020	13	16	9	12	26725	11	11	4	80000	10	26729	26730	26709	26730	26729

LDRSW (register, lsl)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations