Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STP (signed offset, 64-bit)

Test 1: uops

Code:

  stp x0, x1, [x6, #8]
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e1f223f46494f51schedule uop (52)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst int store (96)inst ldst (9b)l1d tlb access (a0)l1d cache miss st (a2)st unit uop (a7)l1d cache writeback (a8)acafbcl1d cache miss st nonspec (c0)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)f5f6f7f8fd
100554240305250160251000100010002242415425423623409100010003000540542111001100010001000010000010022073216235371000543541543543543
100454040015341616025100010001000224241542549353340010001000300054054211100110001000100034100205100203473116225391000541543543543543
100455040915251616025100010001000223521540542355340010001000300054254211100110001000100034100002100203873216225371000543541552541543
1004542403053516160251000100010002235215405513553398100010003000542551111001100010001000010020580100223473216225371000543541552543543
1004542403152716160251000100010002235215405403533408100010003000542551111001100010001000010020210022073216225391000543543541543541
10045424090535160025100010001000224241542542353344410001000300054254211100110001000100034100012100003473216225471000543543543552541
10045404001527160025100010001000224241542542353339810001000300054054911100110001000100034100202100023473316225391000543543543541543
100454040915271616025100010001000224241540550355339810001000300054054211100110001000100034100002100223473116225391000543543541543543
1004540409152701602510001000100022352154255035533981000100030005425421110011000100010003410020810022073216225391000551541543543543
1004540403052716160251000100010002242415405423633400100010003000542542111001100010001000010020210022073216225391000541543543543543

Test 2: throughput

Count: 8

Code:

  stp x0, x1, [x6, #8]
  stp x0, x1, [x6, #8]
  stp x0, x1, [x6, #8]
  stp x0, x1, [x6, #8]
  stp x0, x1, [x6, #8]
  stp x0, x1, [x6, #8]
  stp x0, x1, [x6, #8]
  stp x0, x1, [x6, #8]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)0318191e1f223f46494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int store (96)inst int alu (97)inst ldst (9b)9fl1d tlb access (a0)l1d cache miss st (a2)st unit uop (a7)l1d cache writeback (a8)acafbcl1d cache miss st nonspec (c0)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)? int retires (ef)f5f6f7f8fd
8020540042299000314002716160258010010080000100800005001839784493696240042400422995533000080100200800002002400004004232003118020110099100800001008000010080000348000005800022340051101161140039800001004004340050400434004340043
8020440040299000304003516160258010010080000100800005001839424493696240042400502996332999880100200800002002400004004232007118020110099100800001008000010080000348000202800022340051101161140047800001004004340043400414004340043
8020440040300000314002700325801001008000010080000500183942449369624005140042299633300008010020080000200240000400423199511802011009910080000100800001008000034800020580002200051101161140037800001004004340041400434004140043
8020440040299000004002716160258010010080000100800005001839856493696240042400422995533000080100200800002002400004005031995118020110099100800001008000010080000348000208800002340051101161140039800001004005140043400504004340050
8020440040300000314003616160258010010080000100800005001839808493696240040400422995532999880100200800002002400004004931995118020110099100800001008000010080000348000205800020340051101162140047800001004004340043400434004340043
8020440042300006304010616160258010010080000100800005001839808493696240042400422995533000980100200800002002400004004231995118020110099100800001008000010080000348000002800022340051101161140039800001004004140043400434004340043
8020440050300000314002716160258010010080000100800005001839808493696040042400402995532999880100200800002002400004004232004118020110099100800001008000010080000348000202800022340051101161140047800001004005240043400524004340043
80204400423000003140034160025801001008000010080000500183976049369624004240040299553300008010020080000200240000400503199511802011009910080000100800001008000034800020880002000051101161140039800001004005140043400434004340052
8020440042300000304002716160258010010080000100800005001839352493696040040400402995533000080100200800002002400004005131995118020110099100800001008000010080000348000208800022340051101161140039800001004004140043400434004340051
8020440042299000604002716160258010010080000100800005001839424493696240049400422995533000080100200800002002400004004931995118020110099100800001008000010080000348000208800022340051101161140039800001004004140041400434004340051

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

retire uop (01)cycle (02)03l1d tlb fill (05)mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss data (0b)18191e1f22243a3f46494f51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int store (96)inst int alu (97)inst ldst (9b)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache miss st (a2)a4ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbcl1d cache miss st nonspec (c0)l1d tlb miss nonspec (c1)c2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)dbddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? int retires (ef)f5f6f7f8fd
80025400543001001000171014004816160258001010800001080000501839692049369744005440054299893300438001020800002024000040063400471180021109108000010800001080016144400800140114800021401410502081607740045080000104005540065400484004840055
80024400523001000000200014003201612580010108000010800005018400280493696740047400542998933003480010208000020240000400544005411800211091080000108000010800141444008001601178000216441400502051606640044080000104005540048400484005340055
8002440054300100000022001400321603258001010800001080000501840028049369744005440047299893300278001020800002024000040052400541180021109108000010800001080014150018001401866800021601400502061606540045080000104004840065400554004840055
800244005230010100001810140038161612580010108000010800005018397180493696740048400512998633003480010208000020240000400544006411800211091080000108000010800141544018001601148000016441410502051606840061080000104005540048400494004840064
8002440054300101100017001400321602258001010800001080000501839692049369834005440048299833300278001020800002024000040054400541180021109108000010800001080015164402800161024288000216441410502071609640044080000104062240048400484005540192
800244005430014112112180024003916012580010108000010800005018405081493696740053400542998933003280010208000020240000400524004711800211091080000108000010800151442018001600208000216441400502081607740044080000104004840055400544004840054
800244004730010000001910140039016225800101080000108000050184000404936967400544005229987330034800102080000202400004005440054118002110910800001080000108001515000800160214800001401410502061607740060080000104005440055400554006540055
800244004730010100001710140037161622580010108000010800005018396920493697240047400482998733003480010208000020240000400544005511800211091080000108000010800151444018001600148000214441420502071606640050080000104004840048400554005540055
80024400473001011000171014003716160258001010800001080000501839692049369674005340054299823300328001020800002024000040052400521180021109108000010800001080014160018001602148000216441410503981608840051080000104005240055400544006540048
80024400473001010000170014003916012580010108000010800005018400040493696740054400472998933002780010208000020240000400544004711800211091080000108000010800151444028001602208000216441400502061609740051080000104005540048400644005540048