Firestorm: STP (signed offset, 64-bit) measurements

Code:

  stp x0, x1, [x6, #8]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	22	3f	46	49	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	542	4	0	3	0	525	0	16	0	25	1000	1000	1000	22424	1	542	542	362	3	409	1000	1000	3000	540	542	1	1	1001	1000	1000	1000	0	1000	0	0	1002	2	0	73	2	16	2	3	537	1000	543	541	543	543	543
1004	540	4	0	0	1	534	16	16	0	25	1000	1000	1000	22424	1	542	549	353	3	400	1000	1000	3000	540	542	1	1	1001	1000	1000	1000	34	1002	0	5	1002	0	34	73	1	16	2	2	539	1000	541	543	543	543	543
1004	550	4	0	9	1	525	16	16	0	25	1000	1000	1000	22352	1	540	542	355	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	34	1000	0	2	1002	0	38	73	2	16	2	2	537	1000	543	541	552	541	543
1004	542	4	0	3	0	535	16	16	0	25	1000	1000	1000	22352	1	540	551	355	3	398	1000	1000	3000	542	551	1	1	1001	1000	1000	1000	0	1002	0	580	1002	2	34	73	2	16	2	2	537	1000	543	541	552	543	543
1004	542	4	0	3	1	527	16	16	0	25	1000	1000	1000	22352	1	540	540	353	3	408	1000	1000	3000	542	551	1	1	1001	1000	1000	1000	0	1002	0	2	1002	2	0	73	2	16	2	2	539	1000	543	543	541	543	541
1004	542	4	0	9	0	535	16	0	0	25	1000	1000	1000	22424	1	542	542	353	3	444	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	34	1000	1	2	1000	0	34	73	2	16	2	2	547	1000	543	543	543	552	541
1004	540	4	0	0	1	527	16	0	0	25	1000	1000	1000	22424	1	542	542	353	3	398	1000	1000	3000	540	549	1	1	1001	1000	1000	1000	34	1002	0	2	1000	2	34	73	3	16	2	2	539	1000	543	543	543	541	543
1004	540	4	0	9	1	527	16	16	0	25	1000	1000	1000	22424	1	540	550	355	3	398	1000	1000	3000	540	542	1	1	1001	1000	1000	1000	34	1000	0	2	1002	2	34	73	1	16	2	2	539	1000	543	543	541	543	543
1004	540	4	0	9	1	527	0	16	0	25	1000	1000	1000	22352	1	542	550	355	3	398	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	34	1002	0	8	1002	2	0	73	2	16	2	2	539	1000	551	541	543	543	543
1004	540	4	0	3	0	527	16	16	0	25	1000	1000	1000	22424	1	540	542	363	3	400	1000	1000	3000	542	542	1	1	1001	1000	1000	1000	0	1002	0	2	1002	2	0	73	2	16	2	2	539	1000	541	543	543	543	543

Count: 8

Code:

  stp x0, x1, [x6, #8]
  stp x0, x1, [x6, #8]
  stp x0, x1, [x6, #8]
  stp x0, x1, [x6, #8]
  stp x0, x1, [x6, #8]
  stp x0, x1, [x6, #8]
  stp x0, x1, [x6, #8]
  stp x0, x1, [x6, #8]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	22	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss st (a2)	st unit uop (a7)	l1d cache writeback (a8)	ac	af	bc	l1d cache miss st nonspec (c0)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80205	40042	299	0	0	0	3	1	40027	16	16	0	25	80100	100	80000	100	80000	500	1839784	49	36962	40042	40042	29955	3	30000	80100	200	80000	200	240000	40042	32003	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80000	0	5	80002	2	34	0	0	5110	1	16	1	1	40039	80000	100	40043	40050	40043	40043	40043
80204	40040	299	0	0	0	3	0	40035	16	16	0	25	80100	100	80000	100	80000	500	1839424	49	36962	40042	40050	29963	3	29998	80100	200	80000	200	240000	40042	32007	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80002	0	2	80002	2	34	0	0	5110	1	16	1	1	40047	80000	100	40043	40043	40041	40043	40043
80204	40040	300	0	0	0	3	1	40027	0	0	3	25	80100	100	80000	100	80000	500	1839424	49	36962	40051	40042	29963	3	30000	80100	200	80000	200	240000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80002	0	5	80002	2	0	0	0	5110	1	16	1	1	40037	80000	100	40043	40041	40043	40041	40043
80204	40040	299	0	0	0	0	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839856	49	36962	40042	40042	29955	3	30000	80100	200	80000	200	240000	40050	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80002	0	8	80000	2	34	0	0	5110	1	16	1	1	40039	80000	100	40051	40043	40050	40043	40050
80204	40040	300	0	0	0	3	1	40036	16	16	0	25	80100	100	80000	100	80000	500	1839808	49	36962	40040	40042	29955	3	29998	80100	200	80000	200	240000	40049	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80002	0	5	80002	0	34	0	0	5110	1	16	2	1	40047	80000	100	40043	40043	40043	40043	40043
80204	40042	300	0	0	6	3	0	40106	16	16	0	25	80100	100	80000	100	80000	500	1839808	49	36962	40042	40042	29955	3	30009	80100	200	80000	200	240000	40042	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80000	0	2	80002	2	34	0	0	5110	1	16	1	1	40039	80000	100	40041	40043	40043	40043	40043
80204	40050	300	0	0	0	3	1	40027	16	16	0	25	80100	100	80000	100	80000	500	1839808	49	36960	40042	40040	29955	3	29998	80100	200	80000	200	240000	40042	32004	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80002	0	2	80002	2	34	0	0	5110	1	16	1	1	40047	80000	100	40052	40043	40052	40043	40043
80204	40042	300	0	0	0	3	1	40034	16	0	0	25	80100	100	80000	100	80000	500	1839760	49	36962	40042	40040	29955	3	30000	80100	200	80000	200	240000	40050	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80002	0	8	80002	0	0	0	0	5110	1	16	1	1	40039	80000	100	40051	40043	40043	40043	40052
80204	40042	300	0	0	0	3	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839352	49	36960	40040	40040	29955	3	30000	80100	200	80000	200	240000	40051	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80002	0	8	80002	2	34	0	0	5110	1	16	1	1	40039	80000	100	40041	40043	40043	40043	40051
80204	40042	299	0	0	0	6	0	40027	16	16	0	25	80100	100	80000	100	80000	500	1839424	49	36962	40049	40042	29955	3	30000	80100	200	80000	200	240000	40049	31995	1	1	80201	100	99	100	80000	100	80000	100	80000	34	80002	0	8	80002	2	34	0	0	5110	1	16	1	1	40039	80000	100	40041	40041	40043	40043	40051

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	22	24	3a	3f	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
80025	40054	300	1	0	0	1	0	0	0	17	1	0	1	40048	16	16	0	25	80010	10	80000	10	80000	50	1839692	0	49	36974	40054	40054	29989	3	30043	80010	20	80000	20	240000	40063	40047	1	1	80021	10	9	10	80000	10	80000	10	80016	14	44	0	0	80014	0	1	14	80002	14	0	14	1	0	5020	8	16	0	7	7	40045	0	80000	10	40055	40065	40048	40048	40055
80024	40052	300	1	0	0	0	0	0	0	20	0	0	1	40032	0	16	1	25	80010	10	80000	10	80000	50	1840028	0	49	36967	40047	40054	29989	3	30034	80010	20	80000	20	240000	40054	40054	1	1	80021	10	9	10	80000	10	80000	10	80014	14	44	0	0	80016	0	1	17	80002	16	44	14	0	0	5020	5	16	0	6	6	40044	0	80000	10	40055	40048	40048	40053	40055
80024	40054	300	1	0	0	0	0	0	0	22	0	0	1	40032	16	0	3	25	80010	10	80000	10	80000	50	1840028	0	49	36974	40054	40047	29989	3	30027	80010	20	80000	20	240000	40052	40054	1	1	80021	10	9	10	80000	10	80000	10	80014	15	0	0	1	80014	0	1	866	80002	16	0	14	0	0	5020	6	16	0	6	5	40045	0	80000	10	40048	40065	40055	40048	40055
80024	40052	300	1	0	1	0	0	0	0	18	1	0	1	40038	16	16	1	25	80010	10	80000	10	80000	50	1839718	0	49	36967	40048	40051	29986	3	30034	80010	20	80000	20	240000	40054	40064	1	1	80021	10	9	10	80000	10	80000	10	80014	15	44	0	1	80016	0	1	14	80000	16	44	14	1	0	5020	5	16	0	6	8	40061	0	80000	10	40055	40048	40049	40048	40064
80024	40054	300	1	0	1	1	0	0	0	17	0	0	1	40032	16	0	2	25	80010	10	80000	10	80000	50	1839692	0	49	36983	40054	40048	29983	3	30027	80010	20	80000	20	240000	40054	40054	1	1	80021	10	9	10	80000	10	80000	10	80015	16	44	0	2	80016	1	0	2428	80002	16	44	14	1	0	5020	7	16	0	9	6	40044	0	80000	10	40622	40048	40048	40055	40192
80024	40054	300	1	4	1	1	2	1	12	18	0	0	2	40039	16	0	1	25	80010	10	80000	10	80000	50	1840508	1	49	36967	40053	40054	29989	3	30032	80010	20	80000	20	240000	40052	40047	1	1	80021	10	9	10	80000	10	80000	10	80015	14	42	0	1	80016	0	0	20	80002	16	44	14	0	0	5020	8	16	0	7	7	40044	0	80000	10	40048	40055	40054	40048	40054
80024	40047	300	1	0	0	0	0	0	0	19	1	0	1	40039	0	16	2	25	80010	10	80000	10	80000	50	1840004	0	49	36967	40054	40052	29987	3	30034	80010	20	80000	20	240000	40054	40054	1	1	80021	10	9	10	80000	10	80000	10	80015	15	0	0	0	80016	0	2	14	80000	14	0	14	1	0	5020	6	16	0	7	7	40060	0	80000	10	40054	40055	40055	40065	40055
80024	40047	300	1	0	1	0	0	0	0	17	1	0	1	40037	16	16	2	25	80010	10	80000	10	80000	50	1839692	0	49	36972	40047	40048	29987	3	30034	80010	20	80000	20	240000	40054	40055	1	1	80021	10	9	10	80000	10	80000	10	80015	14	44	0	1	80016	0	0	14	80002	14	44	14	2	0	5020	7	16	0	6	6	40050	0	80000	10	40048	40048	40055	40055	40055
80024	40047	300	1	0	1	1	0	0	0	17	1	0	1	40037	16	16	0	25	80010	10	80000	10	80000	50	1839692	0	49	36967	40053	40054	29982	3	30032	80010	20	80000	20	240000	40052	40052	1	1	80021	10	9	10	80000	10	80000	10	80014	16	0	0	1	80016	0	2	14	80002	16	44	14	1	0	5039	8	16	0	8	8	40051	0	80000	10	40052	40055	40054	40065	40048
80024	40047	300	1	0	1	0	0	0	0	17	0	0	1	40039	16	0	1	25	80010	10	80000	10	80000	50	1840004	0	49	36967	40054	40047	29989	3	30027	80010	20	80000	20	240000	40054	40047	1	1	80021	10	9	10	80000	10	80000	10	80015	14	44	0	2	80016	0	2	20	80002	16	44	14	0	0	5020	6	16	0	9	7	40051	0	80000	10	40055	40048	40064	40055	40048

STP (signed offset, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations