Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMP (uxtw, 32-bit)

Test 1: uops

Code:

  cmp w0, w1, uxtw
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)f5f6f7f8fd
100436930362510001000100050003693692063225100010002000369661110011000073118113661000370370370370370
100436930362510001000100050003693692063225100010002000369661110011000073118113661000370370370370370
100436930362510001000100050003693692063225100010002000369661110011000073118113661000370370370370370
100436920362510001000100050003693692063225100010002000369661110011000073118113661000370370370370370
100436930362510001000100050003693692063225100010002000369661110011000073118113661000370370370370370
100436920362510001000100050003693692063225100010002000369661110011000073118113661000370370370370370
100436930362510001000100050003693692063225100010002000369661110011000073118113661000370370370370370
100436933362510001000100050003693692063225100010002000369661110011000073118113661000370370370370370
100436930362510001000100050003693692063225100010002000369661110011000073118113661000370370370370370
100436930362510001000100050003693692063225100010002000369661110011000073118113661000370370370370370

Test 2: Latency 3->1

Chain cycles: 1

Code:

  cmp w0, w1, uxtw
  cset x0, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20204200351500126119926252010020100201001297150149169552003520035174063174812010020200302002003510411202011009910020100101000013101328221999220000101002003620036200362003620036
2020420035150006119926252010020100201001297150149169552003520035174063174812010020200302002003510411202011009910020100101000013101228221999220000101002003620036200362003620036
2020420035150006119926252010020100201001297150049169552003520035174063174812010020200302002003510411202011009910020100101000613341228221999220000101002003620036200362003620036
2020420035150006119926252010020100201001297790049169552003520035174063174812010020200302002003510411202011009910020100101000013101228221999220000101002003620036200362003620036
20204200351500306119926252010020100201001297150149169552003520035174063174812010020200302002003510411202011009910020100101000013101228221999220000101002003620036200362003620036
2020420035150006119926252010020100201001297150149169552003520035174063174812010020200302002003510411202011009910020100101000013101228221999220000101002003620036200362003620036
2020420035149066119926252010020100201001297150149169552003520035174063174812010020200302002003510411202011009910020100101000013101228221999220000101002003620036200362003620036
202042003515001716119926252010020100201001297150049169552003520035174063174812010020200302002003510411202011009910020100101002013101228221999220000101002003620036200362003620036
2020420035150066119926252010020100201001297150049169552003520035174063174812010020200302002003510411202011009910020100101000013101228221999220000101002003620036200362003620036
2020420035150006119926252010020100201001297150149169552003520035174063174812010020200302002003510411202011009910020100101000013101228221999220000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)03mmu table walk instruction (07)09l2 tlb miss instruction (0a)191e3a3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
200242003515010100211019918252001020010200101297247491695520035200351742831750420010200203002020035104112002110910200101001000127413278171999520000100102003620036200362003620036
200242003515010100268199182520010200102001012972474916955200352003517428317504200102002030020200351041120021109102001010010032531274132713141999520000100102003620036200362008120036
200242003515010100268199182520010200102001012972474916955200352003517428317504200102002030020200351041120021109102001010010031274142712151999520000100102003620036200362003620036
2002420035150101002681991825200102001020010129724749169552003520035174283175042001020020300202003510411200211091020010100100841274152713141999520000100102003620036200362003620036
200242003515010100268199182520010200102001012972474916955200352003517428317504200102002030020200351041120021109102001010010001274152712141999520000100102003620036200362003620036
20024200351501010026819918252001020010200101297247491695520035200351742831750420010200203002020035104112002110910200101001001141274142714141999520000100102003620036200362003620036
20024200351501010026819918252001020010200101297247491695520035200351745631750420010200203002020035104112002110910200101001000127482713141999520000100102003620036200362003620036
200242003515010100268199182520010200102001012972474916955200352003517428317504200102002030020200351041120021109102001010010441621274132714161999520000100102003620036200362003620036
20024200351491010026819918252001020010200101297247491695520035200351742831750420010200203002020035104112002110910200101001000127413276131999520000100102003620036200362003620036
200242003515010100268199182520010200102001012972474916955200352003517428317504200102002030020200351041120021109102001010010001274132714141999520000100102003620036200362003620036

Test 3: Latency 3->2

Chain cycles: 1

Code:

  cmp w0, w1, uxtw
  cset x1, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
202042003515000001200611992625201002010020100129715014916955200352003517406317481201002020030200200351041120201100991002010010100000000013101328221999220000101002003620036200362003620036
20204200351500000000611992625201002010020100129715014916955200352003517406317481201002020030200200351041120201100991002010010100000000013101228231999220000101002003620036200362003620036
20204200351500000000611992625201002010020100129715014916955200352003517406317481201002020030200200351041120201100991002010010100000000013101228221999220000101002003620036200362003620036
20204200351500000000611992625201002010020100129715014916955200352003517406317481201002020030200200351041120201100991002010010100000000013101228221999220000101002003620036200362003620036
20204200351500000600611992625201002010020100129715014916955200352003517406317481201002020030200200351041120201100991002010010100000000013101228221999220000101002003620036200362003620036
20204200351500000000611992625201002010020100129715014916955200352003517406317481201002020030200200351041120201100991002010010100000000013101328221999220000101002003620036200362003620036
2020420035150000000061199262520100201002010012971501491695520035200351740631748120100202003020020035104112020110099100201001010022202818413971266232016520000101002026220261202662008220262
202042026115201545404400128219917642020520234205321299595149171812026520172174492617608204532058130931202631046120201100991002010010100242144003313971275232016520133101002026120264202642026420219
2020420263152005567244001244199171272024020240204501300220149171812026320262174592417614205332077330617202631046120201100991002010010100220024028213791275422016520132101002030720261202612026320219
2020420261152115666044011317199161482023620210206201300255149171752026420261174282717607206072067131064202641046120201100991002010010100420024465213961277232006120111101002021720217200362017120206

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

retire uop (01)cycle (02)031e1f3f4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20024200351500061199182520010200102001012972471491695520035200351742831750420010200203002020035104112002110910200101001000301270227111999520000100102003620036200362003620036
20024200351500061199182520010200102001012972471491695520035200351742831750420010200203002020035104112002110910200101001000001270127111999520000100102003620036200362003620036
20024200351500061199182520010200102001012972471491695520035200351742831750420010200203002020035104112002110910200101001000001270127111999520000100102003620036200362003620036
20024200351500061199182520010200102001012972471491695520035200351742831750420010200203002020035104112002110910200101001000001298127111999520000100102003620036200362003620036
200242003515000232199182520010200102001012972471491695520035200351742831750420010200203002020035104112002110910200101001000001270127111999520000100102003620036200362003620036
20024200351500061199182520010200102001012972471491695520035200351742831750420010200203002020035104112002110910200101001000001270127111999520000100102003620036200362003620036
2002420035150001177199182520010200102001012972471491695520035200351742831750420010200203002020035104112002110910200101001000001270127111999520000100102003620036200362003620036
20024200351500061199182520010200102001012972471491695520035200351742831752720010200203002020035104112002110910200101001000001270127111999520000100102003620036200362003620036
20024200351500061199182520010200102001012972471491695520035200351742831750420010200203002020035104112002110910200101001000301270127111999520000100102003620036200362003620036
20024200351500061199182520010200102001012972471491695520035200351742831750420010200203002020066104112002110910200101001000001270127111999520000100102003620036200362003620036

Test 4: throughput

Count: 8

Code:

  cmp w0, w1, uxtw
  cmp w0, w1, uxtw
  cmp w0, w1, uxtw
  cmp w0, w1, uxtw
  cmp w0, w1, uxtw
  cmp w0, w1, uxtw
  cmp w0, w1, uxtw
  cmp w0, w1, uxtw
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80204267722000352580100801008010040050049236552673526735166723166908010080200160200267356611802011009910080100100051102191126731800001002673626736267362673626736
80204267352000352580100801008010040050049236552673526735166723166908010080200160200267356611802011009910080100100051101191126731800001002673626736267362673626736
80204267352000352580100801008010040050049236552673526735166723166908010080200160200267356611802011009910080100100051101191126731800001002673626736267362673626736
80204267352010352580100801008010040050049236552673526735166723166908010080200160200267356611802011009910080100100051101191126731800001002673626736267362673626736
80204267352000352580100801008010040050049236552673526735166723166908010080200160200267356611802011009910080100100051101191126731800001002673626736267362673626736
80204267352000352580100801008010040050049236552673526735166723166908010080200160200267356611802011009910080100100051101191126731800001002673626736267362673626736
80204267352000352580100801008010040050049236552673526735166723166908010080200160200267356611802011009910080100100051101191126731800001002673626736267362673626736
80204267352000352580100801008010040050049236552673526735166723166908010080200160200267356611802011009910080100100051101191126731800001002673626736267362673626736
802042673520003525801008010080100400500492365526735267351667213166908010080200160200267356611802011009910080100100051101191126731800001002673626736267362673626736
80204267352000352580100801008010040050049236552673526735166723166908010080200160200267356611802011009910080100100351101191126731800001002673626736267362673626736

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

retire uop (01)cycle (02)03mmu table walk data (08)091e1f3f51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)a9accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eb? int retires (ef)f5f6f7f8fd
800242671020000002672580010800108001040005004923625267052670516665316683800108002016002026705661180021109108001010000050203183326701800000102670626706267062670626706
800242670520000007842580010800108001040005004923625267052670516683316683800108002016002026705661180021109108001010000050203183326701800000102670626706267062670626706
800242670520000007212580010800108001040005004923625267052670516665316683800108002016002026705661180021109108001010000050204182426701800000102670626706267062670626706
800242670520000003642580010800108001040037404923625267052670516665316683800108002016002026705661180021109108001010000050203184326701800000102670626706267062670626706
80024267052000000352580010800108001040005004923625267052670516665316683800108002016002026705661180021109108001010000050203182326701800000102670626706267062670626706
80024267052000000562580010800108001040005004923625267052670516665316683800108002016002026705661180021109108001010000050202183226701800000102670626706267062670626706
80024267052000000772580010800108001040005014923625267052670516665316683800108002016002026705661180021109108001010000050203183426701800000102670626706267062670626706
80024267052000000352580010800108001040005004923625267052670516665316683800108002016002026705661180021109108001010000050203183326701800000102670626706267062670626706
80024267052000000352580010800108001040005004923625267052670516665316683800108002016002026705661180021109108001010003050204184326701800000102670626706267062670626706
8002426705201001500276258001080010800104000500492362526705267051666531671480010800201600202670566218002110910800101012453050203183326701800000102670626706267062670626706