Firestorm: CMP (uxtw, 32-bit) measurements

Code:

  cmp w0, w1, uxtw

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	f5	f6	f7	f8	fd
1004	369	3	0	36	25	1000	1000	1000	5000	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	0	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	3	0	36	25	1000	1000	1000	5000	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	0	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	3	0	36	25	1000	1000	1000	5000	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	0	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	2	0	36	25	1000	1000	1000	5000	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	0	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	3	0	36	25	1000	1000	1000	5000	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	0	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	2	0	36	25	1000	1000	1000	5000	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	0	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	3	0	36	25	1000	1000	1000	5000	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	0	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	3	3	36	25	1000	1000	1000	5000	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	0	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	3	0	36	25	1000	1000	1000	5000	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	0	73	1	18	1	1	366	1000	370	370	370	370	370
1004	369	3	0	36	25	1000	1000	1000	5000	369	369	206	3	225	1000	1000	2000	369	66	1	1	1001	1000	0	73	1	18	1	1	366	1000	370	370	370	370	370

Test 2: Latency 3->1

Chain cycles: 1

Code:

  cmp w0, w1, uxtw
  cset x0, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	0	12	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	1310	1	3	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19926	25	20100	20100	20100	1297150	0	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	6	1334	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19926	25	20100	20100	20100	1297790	0	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	30	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	149	0	6	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	171	61	19926	25	20100	20100	20100	1297150	0	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	2	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	6	61	19926	25	20100	20100	20100	1297150	0	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	l2 tlb miss instruction (0a)	19	1e	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	1	0	1	0	0	2	110	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	1274	13	27	8	17	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	1	0	1	0	0	2	68	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	3253	1274	13	27	13	14	19995	20000	10010	20036	20036	20036	20081	20036
20024	20035	150	1	0	1	0	0	2	68	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	3	1274	14	27	12	15	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	1	0	1	0	0	2	68	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	84	1274	15	27	13	14	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	1	0	1	0	0	2	68	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	1274	15	27	12	14	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	1	0	1	0	0	2	68	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	114	1274	14	27	14	14	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	1	0	1	0	0	2	68	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17456	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	1274	8	27	13	14	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	1	0	1	0	0	2	68	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	44	162	1274	13	27	14	16	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	149	1	0	1	0	0	2	68	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	1274	13	27	6	13	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	1	0	1	0	0	2	68	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	1274	13	27	14	14	19995	20000	10010	20036	20036	20036	20036	20036

Test 3: Latency 3->2

Chain cycles: 1

Code:

  cmp w0, w1, uxtw
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	0	0	0	0	12	0	0	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	1310	1	3	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	1310	1	2	28	2	3	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	6	0	0	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	1310	1	2	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	0	0	1310	1	3	28	2	2	19992	20000	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19926	25	20100	20100	20100	1297150	1	49	16955	20035	20035	17406	3	17481	20100	20200	30200	20035	104	1	1	20201	100	99	100	20100	10100	2	2	2	0	2	818	4	1397	1	2	66	2	3	20165	20000	10100	20262	20261	20266	20082	20262
20204	20261	152	0	1	5	4	540	440	0	1282	19917	64	20205	20234	20532	1299595	1	49	17181	20265	20172	17449	26	17608	20453	20581	30931	20263	104	6	1	20201	100	99	100	20100	10100	2	4	2	1	4	4003	3	1397	1	2	75	2	3	20165	20133	10100	20261	20264	20264	20264	20219
20204	20263	152	0	0	5	5	672	440	0	1244	19917	127	20240	20240	20450	1300220	1	49	17181	20263	20262	17459	24	17614	20533	20773	30617	20263	104	6	1	20201	100	99	100	20100	10100	2	2	0	0	2	4028	2	1379	1	2	75	4	2	20165	20132	10100	20307	20261	20261	20263	20219
20204	20261	152	1	1	5	6	660	440	1	1317	19916	148	20236	20210	20620	1300255	1	49	17175	20264	20261	17428	27	17607	20607	20671	31064	20264	104	6	1	20201	100	99	100	20100	10100	4	2	0	0	2	4465	2	1396	1	2	77	2	3	20061	20111	10100	20217	20217	20036	20171	20206

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	3	0	1270	2	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	0	1298	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	232	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	1177	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17527	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20035	104	1	1	20021	10	9	10	20010	10010	0	0	3	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	20035	20035	17428	3	17504	20010	20020	30020	20066	104	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	1	27	1	1	19995	20000	10010	20036	20036	20036	20036	20036

Test 4: throughput

Count: 8

Code:

  cmp w0, w1, uxtw
  cmp w0, w1, uxtw
  cmp w0, w1, uxtw
  cmp w0, w1, uxtw
  cmp w0, w1, uxtw
  cmp w0, w1, uxtw
  cmp w0, w1, uxtw
  cmp w0, w1, uxtw

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	26772	200	0	35	25	80100	80100	80100	400500	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	5110	2	19	1	1	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	200	0	35	25	80100	80100	80100	400500	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	5110	1	19	1	1	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	200	0	35	25	80100	80100	80100	400500	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	5110	1	19	1	1	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	201	0	35	25	80100	80100	80100	400500	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	5110	1	19	1	1	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	200	0	35	25	80100	80100	80100	400500	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	5110	1	19	1	1	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	200	0	35	25	80100	80100	80100	400500	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	5110	1	19	1	1	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	200	0	35	25	80100	80100	80100	400500	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	5110	1	19	1	1	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	200	0	35	25	80100	80100	80100	400500	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	5110	1	19	1	1	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	200	0	35	25	80100	80100	80100	400500	49	23655	26735	26735	16672	13	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	0	5110	1	19	1	1	26731	80000	100	26736	26736	26736	26736	26736
80204	26735	200	0	35	25	80100	80100	80100	400500	49	23655	26735	26735	16672	3	16690	80100	80200	160200	26735	66	1	1	80201	100	99	100	80100	100	3	5110	1	19	1	1	26731	80000	100	26736	26736	26736	26736	26736

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3338

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? int retires (ef)	f5	f6	f7	f8	fd
80024	26710	200	0	0	0	0	267	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	3	18	3	3	26701	80000	0	10	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	0	784	25	80010	80010	80010	400050	0	49	23625	26705	26705	16683	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	3	18	3	3	26701	80000	0	10	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	0	721	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	4	18	2	4	26701	80000	0	10	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	0	364	25	80010	80010	80010	400374	0	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	3	18	4	3	26701	80000	0	10	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	0	35	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	3	18	2	3	26701	80000	0	10	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	0	56	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	2	18	3	2	26701	80000	0	10	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	0	77	25	80010	80010	80010	400050	1	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	3	18	3	4	26701	80000	0	10	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	0	35	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	3	18	3	3	26701	80000	0	10	26706	26706	26706	26706	26706
80024	26705	200	0	0	0	0	35	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	3	16683	80010	80020	160020	26705	66	1	1	80021	10	9	10	80010	10	0	0	3	0	5020	4	18	4	3	26701	80000	0	10	26706	26706	26706	26706	26706
80024	26705	201	0	0	150	0	276	25	80010	80010	80010	400050	0	49	23625	26705	26705	16665	3	16714	80010	80020	160020	26705	66	2	1	80021	10	9	10	80010	10	1	2	453	0	5020	3	18	3	3	26701	80000	0	10	26706	26706	26706	26706	26706

CMP (uxtw, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations