Firestorm: LDP (pre-index, 64-bit) measurements

Code:

  ldp x0, x1, [x6, #8]!

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 3.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	1e	20	22	23	29	2b	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int load (95)	inst ldst (9b)	9d	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	ldst x64 uop (b1)	b5	b6	bb	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
3005	1052	8	1	1	1	0	70	20	0	0	0	0	2	0	1025	19	3	5	5	18	25	2000	1000	1000	1000	1000	52835	45590	1	1040	1040	576	3	648	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	0	1016	7	0	77	1058	10	0	13	0	40	1043	125	39	6	32	43	7	0	0	73	2	16	2	2	1036	0	1000	22	14	1000	2000	1041	1041	1041	1041	1041
3004	1040	7	1	1	1	0	77	34	0	0	0	0	5	8	1025	12	6	7	12	26	25	2000	1000	1000	1000	1000	52836	45590	0	1061	1042	576	3	648	2151	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	0	1028	7	0	55	1050	7	0	11	6	39	1045	125	31	5	45	59	7	1	0	73	2	16	2	2	1036	0	1000	26	25	1000	2000	1041	1041	1041	1041	1041
3004	1040	8	1	0	1	0	92	0	0	0	0	0	2	0	1025	12	11	11	4	26	25	2000	1000	1000	1000	1000	52828	45589	1	1040	1040	576	3	648	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	0	1026	6	2	50	1040	11	0	20	10	27	1027	125	34	5	43	43	6	2	0	73	2	16	2	2	1036	0	1000	21	20	1000	2000	1041	1041	1041	1041	1041
3004	1040	7	1	1	1	0	68	22	0	0	0	0	4	0	1025	16	1	10	6	21	25	2000	1000	1000	1000	1000	52852	45590	1	1040	1040	574	3	648	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	0	1021	7	1	61	1053	8	0	26	6	50	1055	125	45	6	32	85	7	0	1	73	2	16	2	2	1037	0	1000	24	30	1000	2000	1041	1041	1041	1041	1041
3004	1040	7	1	1	0	0	47	16	1	0	0	0	3	12	1025	0	0	4	2	21	25	2000	1000	1000	1000	1000	52835	45590	1	1040	1040	574	3	648	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	0	1022	7	1	60	1037	4	0	16	4	37	1036	125	22	3	26	51	7	0	0	73	2	16	2	2	1037	1	1000	14	19	1000	2000	1041	1041	1041	1041	1041
3004	1040	7	1	1	1	0	74	16	1	0	0	0	2	0	1025	12	1	9	8	18	25	2000	1000	1000	1000	1000	52820	45588	0	1040	1040	574	3	648	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	0	1026	8	2	59	1048	4	0	14	10	40	1033	125	35	4	38	43	7	1	1	73	2	16	2	2	1037	0	1000	24	23	1000	2000	1041	1041	1041	1041	1041
3004	1040	7	1	1	1	0	69	20	0	0	0	0	1	0	1025	16	5	16	6	17	25	2000	1000	1000	1000	1000	52833	45591	1	1040	1040	574	3	648	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	0	1024	6	3	69	1057	4	0	10	0	42	1041	125	28	4	58	34	6	0	0	73	2	16	2	2	1037	0	1000	22	14	1000	2000	1041	1041	1041	1041	1041
3004	1040	8	1	1	0	0	57	10	0	0	0	0	2	0	1025	8	2	0	5	10	25	2000	1000	1000	1000	1000	52862	45590	1	1040	1040	574	3	648	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	0	1055	7	1	40	1037	12	1	11	0	29	1026	125	25	5	33	51	6	0	0	73	2	16	2	2	1037	1	1000	30	21	1000	2000	1041	1041	1041	1041	1041
3004	1040	8	1	0	0	1	112	22	0	0	0	0	2	0	1046	0	2	2	4	14	25	2000	1000	1000	1000	1000	52852	45591	1	1040	1040	574	3	648	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	0	1007	7	0	79	1045	0	0	1	0	26	1038	125	32	6	36	68	7	0	0	73	2	16	2	2	1037	0	1000	20	27	1000	2000	1041	1041	1041	1041	1041
3004	1040	7	1	0	0	0	57	15	1	0	0	0	4	0	1025	12	2	3	4	17	25	2000	1000	1000	1000	1000	52825	45590	0	1040	1054	574	3	648	2000	1000	2000	1000	1000	1040	38	1	1	1001	1000	1000	0	1039	7	1	34	1052	15	0	16	6	45	1047	125	31	4	35	52	6	1	0	73	2	16	2	2	1037	0	1000	14	14	1000	2000	1041	1041	1043	1041	1041

Test 2: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldp x0, x1, [x6, #8]!
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.8450

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	0e	0f	18	19	1e	1f	20	22	23	3a	3f	40	43	46	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	ldst x64 uop (b1)	ldst xpg uop (b2)	b5	bb	be	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60209	83543	593	1	0	1	0	0	0	0	0	315	0	7	1	0	532	79260	7	13	0	6	77732	25	52845	42196	11020	40100	10000	672640	2959604	0	49	74879	78177	78680	70794	3	73486	50100	40200	20000	70200	10000	77965	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10020	3	560	10033	0	16	8	25	10033	1250	4	616	23	4	515	1	2	0	2610	2	72	1	1	78284	42168	5499	5612	4726	10000	50100	78862	78767	79530	78365	79205
60204	79553	586	1	0	2	0	0	0	0	0	311	0	5	2	0	514	78485	9	15	0	9	79867	578	53088	42465	10653	42871	10743	714844	3067156	0	49	76286	79729	79740	70702	195	73579	53479	43464	21662	75426	10829	80368	35	19	1	40201	100	99	100	10000	30100	10000	0	100	10124	7	489	10089	0	16	11	36907	10091	1257	4	495	26	4	499	1	0	0	3004	1	250	2	1	79812	42301	5286	5069	5042	10000	50100	80273	80317	79898	80611	80731
60204	79776	609	1	0	0	0	0	0	24	23	3237	1994	10	2	0	543	79755	9	16	1	10	79903	25	52635	42308	10526	40100	10000	675484	2989163	0	49	75944	78175	78526	71370	243	74777	53457	40200	20494	77173	11043	80812	35	9	1	40201	100	99	100	10000	30100	10000	0	100	10084	1	555	10118	0	18	9	29	10032	1250	4	462	30	4	520	1	0	0	3104	1	296	2	1	80294	42408	5321	5299	5371	10000	50100	81039	80590	80952	81011	80427
60204	80144	605	1	2	1	2	0	1	20	22	3247	704	7	1	0	448	78084	6	15	2	6	78577	189	53262	42124	10536	41266	10367	693833	3017961	0	49	76616	78836	78362	70332	3	72987	50100	40200	20000	70200	10000	78593	35	2	1	40201	100	99	100	10000	30100	10000	0	100	10075	1	516	10092	0	9	7	36635	10093	1259	4	481	32	4	547	1	3	0	2630	1	57	1	1	79036	42160	5184	5079	5155	10000	50100	78014	78593	78579	78154	78350
60204	78722	588	1	1	0	2	0	0	10	8	1419	778	5	1	0	485	78237	5	15	0	9	78239	25	52680	42176	10503	40100	10049	687274	3002930	0	49	75555	78633	78149	70416	3	72847	50100	40200	20000	70200	10000	78464	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10016	1	509	10032	0	11	6	24	10029	1250	4	496	23	4	488	1	0	0	2610	1	57	1	1	77821	42104	5254	5260	5521	10000	50100	78390	79191	78361	78002	80692
60204	78231	583	1	0	0	0	0	1	0	0	316	0	10	1	0	489	78304	6	15	0	6	77716	25	52890	42224	10542	40100	10000	682738	3003628	0	49	75362	78531	78482	70752	3	72575	50100	40200	20000	70200	10000	78424	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10016	2	485	10034	0	11	7	24	10030	1250	4	466	24	4	501	1	0	0	2610	1	57	1	1	78060	42180	5090	6251	5691	10000	50100	78485	78531	78441	78645	79347
60204	78405	587	1	0	0	0	0	0	0	0	318	0	10	1	0	463	78013	6	15	0	6	78477	25	52650	42084	10522	40100	10000	677653	2995211	0	49	75323	78371	77851	70091	3	73479	50100	40368	20000	70200	10000	77936	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10018	2	550	10033	0	9	7	25	10033	1250	4	520	25	4	522	1	2	0	2610	1	57	1	1	78681	41928	5102	5135	5590	10000	50100	79002	78513	78018	77880	78316
60204	77967	584	1	0	0	1	0	0	0	0	324	0	9	2	0	528	78686	7	19	1	6	78823	25	53045	42308	10537	40100	10000	677050	2993541	0	49	75430	78693	78386	70752	3	73898	50100	40200	20000	70200	10000	79209	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10017	1	504	10034	0	17	10	30	10029	1250	4	521	24	4	511	1	1	0	2610	1	57	1	1	77967	42208	5320	5214	5333	10000	50100	78755	78808	78447	78956	79410
60204	78489	587	1	0	0	0	0	1	0	0	304	0	5	1	0	500	78543	7	15	0	8	78495	25	52820	42236	10514	40100	10000	673864	2996660	0	49	75693	78240	78736	72613	3	72937	50100	40200	20000	70200	10000	78904	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10018	1	554	10037	0	12	10	30	10033	1250	4	521	25	4	534	1	0	0	2610	1	57	1	1	78374	42124	5217	4801	5134	10000	50100	78261	78532	78205	78290	78453
60204	78271	589	1	1	1	0	0	0	0	0	319	0	7	1	0	507	78815	10	16	1	9	78514	25	52845	42268	10536	40100	10000	679462	3003020	0	49	76616	78689	78302	71541	3	72984	50100	40200	20000	70200	10000	78691	35	1	1	40201	100	99	100	10000	30100	10000	0	100	10019	1	535	10030	0	10	8	24	10029	1250	4	518	23	4	489	1	0	0	2610	1	57	1	1	78593	42212	5009	5046	5656	10000	50100	78581	78428	78491	78106	78453

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.8790

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	0f	19	1e	1f	20	22	24	3a	3f	40	43	46	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	ldst x64 uop (b1)	ldst xpg uop (b2)	b5	bb	be	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60029	83848	599	2	2	0	0	0	0	155	0	7	1	0	506	79236	9	2	1	0	78495	25	53575	42174	10616	40010	10000	683948	3010729	0	49	75807	78966	78955	70754	3	71304	50212	40020	20000	70020	10000	79482	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10019	4	516	10057	29	5	22	10017	1250	4	606	13	4	512	3	0	0	0	2520	2	64	2	2	78497	41872	5144	5681	6136	10000	50010	79350	78581	78552	78336	78336
60024	78380	595	4	0	0	0	0	0	159	0	7	1	0	497	78811	10	2	0	2	78245	25	52695	41946	10472	40010	10000	675830	2988826	0	49	75565	79152	79477	70625	3	71692	50010	40020	20000	70020	10000	79076	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10023	6	536	10023	18	13	22	10020	1250	4	506	13	4	501	3	0	0	0	2520	3	83	2	2	78115	42260	5979	5604	5472	10000	50010	78866	78224	78310	78341	78461
60024	78811	594	3	0	3	0	0	0	138	0	9	1	0	499	78684	9	2	1	2	78534	25	52763	42114	10499	40010	10000	681775	3027664	0	49	75685	79220	79067	71367	3	71516	50010	40020	20000	70020	10000	79413	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10018	6	522	10043	37	12	22	10017	1250	4	546	13	4	490	3	4	0	0	2520	2	83	2	2	78282	42276	5848	5653	5556	10000	50010	78401	78499	78306	78393	78382
60024	78565	587	3	3	3	0	0	0	274	264	9	1	0	537	78745	11	3	0	3	78639	25	52660	42034	10598	40010	10000	675989	2999215	1	49	75455	78936	79331	71856	3	70953	50010	40020	20000	70020	10000	78754	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10018	6	574	10023	11	10	19	10021	1250	4	491	13	4	517	3	0	0	0	2520	2	83	2	2	78419	42252	5719	5559	5579	10000	50010	79536	79409	79073	79222	79840
60024	78463	588	3	0	0	0	0	0	148	0	7	1	0	529	79039	7	2	0	2	78955	25	52718	42030	10522	40010	10000	682621	3024217	0	49	75602	79321	79681	70984	3	70937	50010	40020	20000	70020	10000	79196	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10018	6	499	10044	15	7	25	10017	1250	4	501	13	4	554	3	0	0	0	2520	2	83	2	2	78687	42132	5639	5513	5671	10000	50010	78885	78818	78085	78557	79945
60024	79167	588	3	0	0	0	0	0	130	0	8	1	0	492	78156	7	2	0	2	79324	25	52640	42110	10546	40010	10000	676690	3011330	1	49	76101	79534	79017	71211	3	71379	50010	40020	20000	70020	10000	78893	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10023	3	494	10023	39	16	27	10021	1250	4	502	16	4	505	3	3	0	0	2520	3	83	2	2	78488	42120	5663	5590	5628	10000	50010	79177	78707	79012	78584	79146
60024	79263	593	3	0	3	0	0	0	160	0	7	1	0	495	78828	10	2	0	2	79143	25	52599	42178	10495	40010	10000	681919	3008298	1	49	75573	78449	78534	71102	3	71311	50010	40020	20000	70020	10000	78356	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10017	6	483	10022	14	6	18	10018	1250	4	479	12	4	489	2	2	0	0	2520	2	83	2	2	79144	42004	5507	5761	5639	10000	50010	79668	79675	79428	79048	78759
60024	78652	592	2	0	0	0	0	0	133	0	9	1	0	531	78503	9	2	0	2	79073	25	52730	42142	10500	40010	10000	679978	3010987	0	49	75363	79294	79245	70871	3	71274	50010	40020	20000	70020	10000	79515	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10026	2	524	10024	20	11	34	10016	1250	4	507	11	4	469	1	0	0	0	2520	2	17	2	2	78278	42032	5783	5502	5694	10000	50010	79106	78986	78957	78885	78833
60024	78984	595	2	2	0	0	0	0	152	0	10	1	0	531	78774	10	2	0	2	78840	25	52690	42118	10497	40010	10000	681598	3007832	1	49	75744	78774	78716	71232	3	71207	50010	40020	20000	70020	10000	78773	35	1	1	40021	10	9	10	10000	30010	10000	1	10	10021	2	509	10022	21	13	14	10017	1250	4	469	12	4	499	2	0	0	0	2520	2	83	2	2	78753	42124	6130	5584	5373	10000	50010	78711	78735	78724	78888	79821
60024	78977	595	2	2	0	0	0	0	137	0	7	1	0	517	79205	7	2	0	2	78292	25	52615	42054	10531	40158	10000	678284	3032039	1	49	75870	78673	77959	71005	3	71164	50010	40020	20000	70314	10000	78349	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10017	4	485	10023	16	12	15	10019	1251	4	489	12	4	490	2	0	0	0	2520	3	83	2	3	78765	41932	5422	5686	6121	10000	50010	78257	79324	78539	78409	78643

Test 3: Latency 2->3 (with chain penalty)

Chain cycles: 3

Code:

  ldp x0, x1, [x6, #8]!
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.8579

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	0e	0f	1e	20	22	23	24	3a	3f	40	43	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	ldst x64 uop (b1)	ldst xpg uop (b2)	b5	bb	be	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60209	83251	595	0	0	0	325	11	1	0	0	495	78473	6	4	2	78109	25	52535	42112	10639	40256	10000	679583	2988602	1	49	75345	0	78379	78946	70405	3	71427	50100	40200	20000	70200	10000	78218	35	1	1	40201	100	99	100	10000	30100	10000	100	10017	525	10022	19	8	15	10020	1250	4	638	16	4	519	2610	2	73	1	1	78453	42028	5167	4973	5166	10000	50100	78870	78570	79172	78740	78486
60204	78317	587	0	0	1	368	9	1	0	0	518	78560	10	5	5	78198	25	52760	42204	10548	40100	10000	685685	3021268	0	49	75469	0	78531	78736	71257	3	71646	50100	40200	20000	70200	10000	77849	35	1	1	40201	100	99	100	10000	30100	10000	100	10015	507	10020	10	9	18	10021	1250	4	497	14	4	523	2610	1	73	1	1	78534	42236	5431	5232	5206	10000	50100	78600	78468	78649	78371	78395
60204	79021	596	0	0	0	332	9	1	0	0	510	77996	7	4	3	78290	25	52830	42224	10506	40100	10000	677261	2995914	0	49	75718	0	77997	78236	71162	3	70588	50100	40200	20000	70200	10000	78623	35	1	1	40201	100	99	100	10000	30100	10000	100	10017	567	10020	10	9	16	10020	1250	4	509	13	4	562	2610	1	73	1	1	78200	42060	5423	5069	5203	10000	50100	78501	78328	78036	78328	78288
60204	78239	593	0	0	0	340	9	1	0	0	516	78031	9	4	5	77919	25	52695	42192	10508	40100	10000	677576	2992039	0	49	75769	0	78805	78659	70245	3	71305	50100	40200	20000	70200	10000	77562	35	1	1	40201	100	99	100	10000	30100	10000	100	10017	495	10023	15	9	14	10050	1250	4	504	12	4	525	2610	1	73	1	1	78338	42048	4880	5204	5816	10000	50100	78605	78617	78831	78446	79101
60204	78292	613	0	0	0	355	11	1	0	0	478	77955	7	4	4	78097	25	52755	42188	10531	40100	10000	678089	2994510	0	49	75063	0	78174	77953	70617	3	70632	50100	40200	20000	70200	10000	78705	35	1	1	40201	100	99	100	10000	30100	10000	100	10014	549	10042	10	10	16	10019	1250	4	519	13	4	513	2610	1	73	1	1	78145	42072	4859	5300	5347	10000	50100	78202	78473	78277	78132	78317
60204	78279	586	0	0	0	297	10	1	0	0	491	78102	9	5	5	77842	25	52625	42104	10503	40100	10000	676802	3005331	0	49	74854	0	78091	78782	70584	3	70841	50100	40200	20000	70200	10000	77624	35	1	1	40201	100	99	100	10000	30100	10000	100	10017	494	10022	12	7	11	10022	1250	4	497	13	4	492	2610	1	73	1	1	78411	41932	4925	5251	6748	10000	50100	78671	78627	78928	78661	78564
60204	78134	590	0	0	0	312	11	1	0	0	517	78574	6	4	4	79098	25	52690	42232	10554	40100	10000	675506	2994643	0	49	75571	0	79102	78818	70379	3	71028	50301	40200	20000	70200	10000	78542	35	1	1	40201	100	99	100	10000	30100	10000	100	10018	525	10017	9	9	12	10023	1250	4	576	13	4	526	2610	1	73	1	1	78306	42092	5111	4926	5276	10000	50100	77980	78623	78522	78436	78439
60204	78508	586	0	0	0	340	9	1	0	0	489	78347	10	5	4	77477	25	52650	42348	10487	40100	10000	675785	2999625	0	49	75422	0	78308	78925	71371	3	71026	50100	40200	20000	70200	10000	78709	35	1	1	40201	100	99	100	10000	30100	10000	100	10014	522	10020	11	7	15	10020	1250	4	550	12	4	518	2610	1	73	1	1	79021	42240	5082	5208	5436	10000	50100	78778	78427	78615	78751	79515
60204	79095	589	0	0	0	329	10	1	0	0	532	78318	7	5	4	78299	44	53475	42276	10524	40100	10000	684722	3015974	0	49	75474	0	78141	78136	70954	3	71422	50100	40200	20000	70200	10000	78360	35	1	1	40201	100	99	100	10000	30100	10000	100	10017	513	10022	14	9	16	10022	1250	4	507	13	4	530	2610	1	73	1	1	78186	42128	5211	5180	5209	10000	50100	78546	78758	80007	78273	78812
60204	78223	583	0	0	0	332	10	1	0	0	491	78620	10	6	3	78396	25	52935	42172	10553	40100	10000	681104	3011234	0	49	76000	0	78678	78533	70476	3	71189	50100	40200	20000	70200	10000	78116	35	1	1	40201	100	99	100	10000	30100	10000	100	10015	558	10019	19	7	14	10021	1250	4	481	13	4	535	2610	1	73	1	1	78399	42192	5499	5352	5911	10000	50100	78237	78175	78411	78182	78818

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.8836

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	0e	0f	18	19	1e	20	22	23	24	3a	3f	40	43	46	49	4d	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss ld (a3)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	af	ldst x64 uop (b1)	ldst xpg uop (b2)	b5	bb	be	l1d cache miss ld nonspec (bf)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
60029	82837	600	1	0	0	0	151	10	1	0	0	496	78694	7	1	0	0	81327	25	52600	42170	10636	40010	10000	681616	3043540	0	49	75560	0	78562	78549	70725	0	3	71108	50010	40020	20000	70020	10000	79032	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10017	0	574	10018	10	10	21	10018	1250	4	632	9	4	520	2520	2	64	2	2	78739	42104	5455	5326	5449	10000	50010	78996	79193	81581	78920	79102
60024	78664	592	0	0	0	0	152	9	1	0	0	496	79142	9	1	0	1	81222	25	52640	42058	10507	40010	10000	675487	3043691	1	49	75605	0	79623	79087	70794	0	3	71137	50010	40020	20000	70020	10000	78854	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10015	0	535	10020	8	10	18	10019	1250	4	517	9	4	517	2520	2	64	2	2	78515	42092	5470	5255	5362	10000	50010	78659	78645	81604	79373	79308
60024	78506	584	0	0	0	0	127	7	1	0	0	489	78699	7	1	0	1	80150	25	52800	42174	10521	40010	10000	683119	3024063	1	49	75967	0	78504	78549	71440	0	3	71835	50010	40020	20000	70020	10000	78888	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10015	0	530	10018	13	7	12	10016	1250	4	551	9	4	500	2520	2	64	2	2	79078	41960	5534	5631	5503	10000	50010	78423	78521	81337	79411	79203
60024	78820	587	0	0	0	0	136	7	1	0	0	535	79045	7	1	0	1	81086	25	52520	42082	10549	40010	10000	682354	3008467	1	49	75043	0	78683	79064	70455	0	3	71252	50010	40020	20000	70020	10000	78366	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10017	0	539	10018	14	9	33	10016	1250	4	474	9	4	504	2520	2	64	2	2	78387	41968	5451	5406	5242	10000	50010	78585	79104	80949	78717	78234
60024	78744	588	0	0	0	0	127	7	1	0	0	485	79519	7	1	0	0	81349	25	52690	42026	10495	40010	10000	679159	3014413	1	49	76088	0	78706	78416	71464	0	3	71065	50010	40020	20000	70020	10000	78518	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10014	0	547	10016	16	7	21	10016	1250	4	512	10	4	510	2520	2	64	2	2	78577	42064	5653	5829	5464	10000	50010	79766	79162	81055	79560	79029
60024	78580	587	0	0	0	0	143	10	1	0	0	489	79045	7	1	0	1	80619	25	52680	41974	10488	40010	10000	681301	3017729	1	49	75404	0	79359	78437	70518	0	3	70584	50010	40020	20000	70020	10000	78308	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10017	0	503	10018	10	9	24	10016	1250	4	507	9	4	513	2520	2	64	3	2	78189	42108	6092	6054	6071	10000	50010	79062	79307	81005	80020	78742
60024	78780	595	0	0	0	0	136	7	1	0	0	450	78833	6	1	0	0	81831	25	52620	42090	10559	40010	10000	682693	3023025	1	49	75733	0	78786	78474	70904	0	3	70883	50010	40020	20000	70020	10000	78661	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10014	0	587	10016	16	9	24	10016	1250	4	512	9	4	489	2520	2	83	2	2	78485	41960	5338	5242	5255	10000	50010	78564	78934	81612	79418	78910
60024	79061	594	0	0	0	0	132	7	1	0	0	529	78889	10	1	0	0	81037	25	52770	42042	10524	40010	10000	680533	2995392	1	49	75848	0	79152	78755	71173	0	3	71710	50010	40020	20000	70020	10000	79008	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10017	0	550	10016	17	7	19	10016	1250	4	536	9	4	484	2520	2	83	2	2	78860	42120	5936	5757	6109	10000	50010	79644	78811	81678	79341	79082
60025	80075	601	0	0	0	0	141	7	1	0	0	509	78935	9	1	0	1	80852	25	52625	42014	10505	40010	10000	678121	3008902	1	49	75515	0	78726	78457	70481	0	3	70978	50010	40020	20000	70020	10000	78414	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10015	0	567	10015	14	6	24	10017	1250	4	517	9	4	542	2520	2	83	2	2	78490	42208	5719	6370	5691	10000	50010	78239	79175	81887	79667	79114
60024	78600	589	0	0	0	0	171	7	1	0	0	480	79239	7	1	0	1	81695	25	52585	42174	10495	40010	10000	680470	3048342	0	49	75775	0	78874	79708	71555	0	3	71537	50010	40020	20000	70020	10000	78767	35	1	1	40021	10	9	10	10000	30010	10000	0	10	10017	0	580	10016	12	7	21	10015	1250	4	470	9	4	503	2520	2	83	2	2	78431	42052	5567	5518	5603	10000	50010	79489	79021	81246	79342	79388

Test 4: throughput

Count: 8

Code:

  ldp x0, x1, [x6, #8]!
  ldp x0, x1, [x7, #8]!
  ldp x0, x1, [x8, #8]!
  ldp x0, x1, [x9, #8]!
  ldp x0, x1, [x10, #8]!
  ldp x0, x1, [x11, #8]!
  ldp x0, x1, [x12, #8]!
  ldp x0, x1, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.4071

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0e	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6b	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	ldst x64 uop (b1)	ldst xpg uop (b2)	b5	b6	bb	be	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240209	32708	243	2	0	0	1	7476	805	1	680	428	140	32301	790	577	1710	1729	1403	776	160127	80131	80000	80100	80000	400577	666384	0	23	49	29340	0	32489	32397	1494	1229	3	2517	160100	80200	160000	80200	80000	32384	38	1	1	80201	100	99	2	100	80000	100	80000	0	100	81022	24	447	5055	85286	828	14	867	80	5808	86058	10000	32	663	108	5413	32	5055	31	0	5	5110	2	16	2	2	32239	150	80026	497	427	2	80000	160100	32548	32707	32535	32529	32641
240204	32750	243	3	3	0	0	7037	792	1	688	474	136	32371	806	573	1734	1720	1451	775	160124	80117	80000	80100	80000	400577	686718	0	29	49	29516	0	32513	32426	1753	1152	3	2322	160100	80200	160000	80200	80000	32487	38	1	1	80201	100	99	9	100	80000	100	80000	0	100	80961	55	443	5473	85510	788	11	907	32	5079	86031	10000	32	684	132	5514	32	4852	47	0	0	5110	2	16	2	2	32363	166	80029	422	378	3	80000	160100	32463	32481	32697	32563	32465
240204	32509	241	3	0	0	0	6674	785	1	720	428	144	32393	807	516	1697	1753	1394	803	160117	80119	80000	80100	80000	400602	677371	0	27	49	29491	0	32511	32199	1784	1061	3	2341	160100	80200	160000	80200	80000	32488	38	1	1	80201	100	99	25	100	80000	100	80000	0	100	81049	47	447	4899	85415	794	9	900	32	5021	86227	10000	32	619	115	5311	32	5307	48	0	1	5110	2	16	2	2	32690	143	80032	473	486	1	80000	160100	32590	32630	32491	32680	32332
240204	32712	243	4	0	0	0	6861	782	1	688	428	132	32638	766	567	1999	1793	1286	799	160120	80123	80000	80100	80000	400568	694124	0	30	49	29597	0	32713	32632	1464	1325	3	2466	160100	80653	160000	80200	80000	32398	38	1	1	80201	100	99	7	100	80000	100	80000	0	100	81090	68	425	5465	85737	867	25	902	44	5695	86525	10000	32	643	121	5315	32	5215	66	0	3	5110	2	16	2	2	32474	169	80015	437	374	0	80000	160100	32671	32470	32515	32584	32503
240204	32515	242	3	0	0	0	7092	811	1	688	427	132	32253	767	514	1734	1808	1307	765	160124	80119	80000	80100	80000	400568	683829	0	32	49	29585	0	32444	32439	1697	990	3	2559	160100	80200	160000	80200	80000	32688	38	1	1	80201	100	99	18	100	80000	100	80000	0	100	81016	49	443	4952	85916	863	9	929	46	6220	86498	10000	32	639	132	5438	32	5156	49	4	4	5110	2	16	2	2	32620	163	80031	472	383	7	80000	160100	32546	32686	32651	32746	32537
240204	32728	246	4	0	4	0	7335	847	1	712	453	132	32603	789	553	1770	1688	1415	814	160121	80131	80000	80100	80000	400568	662077	0	20	49	29564	0	32717	32722	1636	1049	3	2302	160100	80200	160000	80200	80000	32435	38	1	1	80201	100	99	4	100	80000	100	80000	0	100	81026	68	435	4628	85287	813	9	902	32	5672	85984	10000	32	665	123	5574	32	5024	64	4	7	5110	2	16	2	2	32301	163	80023	445	517	8	80000	160100	32432	32424	32532	32733	32441
240204	32657	244	3	0	0	0	8016	822	1	736	359	104	32418	803	533	1805	1691	1352	791	160126	80125	80000	80100	80000	400602	670910	0	29	49	29530	0	32441	32572	1544	1107	3	2649	160100	80200	160000	80200	80000	32367	38	1	1	80201	100	99	23	100	80000	100	80000	0	100	81011	48	431	5401	85467	824	11	911	40	5329	86979	10000	32	683	119	5814	32	5246	46	0	3	5110	2	16	2	2	32494	172	80026	469	484	2	80000	160100	32684	32650	32492	32590	32477
240204	32481	244	3	0	0	0	7006	787	1	616	444	136	32524	746	498	1576	1872	1491	806	160127	80123	80000	80100	80000	400561	656910	0	24	49	28906	0	32539	32721	1541	1200	3	2509	160100	80200	160000	80200	80000	32718	38	1	1	80201	100	99	6	100	80000	100	80000	0	100	81025	48	469	4555	85216	827	10	911	80	5416	85761	10000	32	605	117	5590	32	4962	16	1	0	5110	2	16	2	2	32440	153	80025	497	491	0	80000	160100	32794	32476	32424	32437	32628
240204	32394	244	4	0	4	0	7524	777	1	720	488	100	32662	744	497	1793	1533	1170	798	160123	80126	80000	80100	80000	400570	673574	0	29	49	29231	0	32197	32699	1485	1022	61	2390	160100	80200	160000	80200	80000	32283	38	1	1	80201	100	99	15	100	80000	100	80000	0	100	81029	66	471	4780	85591	803	10	920	80	5417	86128	10000	32	635	119	5123	32	5034	63	20	7	5110	2	16	2	2	32507	147	80029	482	439	2	80000	160100	32532	32567	32490	32440	32536
240204	32298	243	3	3	0	0	7480	799	1	704	412	104	32417	789	545	1716	1443	1409	787	160128	80123	80000	80100	80000	400584	688134	0	29	49	29267	0	32582	32483	1642	1056	3	2288	160100	80200	160000	80200	80000	32588	38	1	1	80201	100	99	15	100	80000	100	80000	0	100	81012	68	474	5032	85855	838	8	880	84	5954	86270	10000	32	665	122	5286	32	4506	64	0	0	5110	2	16	2	2	32360	136	80031	481	491	9	80000	160100	32416	32771	32579	32385	32852

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.4058

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	0f	1e	20	22	29	3a	3e	3f	40	43	46	49	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	5f	60	67	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int load (95)	inst int alu (97)	inst ldst (9b)	9d	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ab	ac	af	ldst x64 uop (b1)	ldst xpg uop (b2)	b5	b6	bb	be	l1d cache miss ld nonspec (bf)	l1d tlb miss nonspec (c1)	c2	c3	cf	d5	map dispatch bubble (d6)	da	db	dd	fetch restart (de)	e0	e7	? int output thing (e9)	ea	eb	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
240029	32757	243	0	0	0	0	6634	815	1	736	446	104	32261	792	520	1688	1860	1337	816	160038	80036	80000	80010	80000	400133	658625	0	0	31	49	29650	32791	32517	1344	1178	3	2416	160010	80020	160000	80020	80000	32509	38	1	1	80021	10	9	10	10	80000	10	80000	1	10	80952	17	475	5509	85423	777	11	896	74	6362	86595	10000	32	728	124	5502	32	4334	16	1	4	5020	9	16	0	0	3	6	32377	150	80029	423	457	2	80000	160010	32556	32301	32508	32603	32766
240024	32357	243	1	0	0	0	6395	825	1	728	440	120	32650	769	583	1845	1926	1336	820	160037	80031	80000	80010	80000	400164	676020	0	0	25	49	29495	32562	32432	1409	1002	3	2708	160010	80020	160000	80020	80000	32544	38	1	1	80021	10	9	15	10	80000	10	80000	1	10	81011	31	462	4942	86179	859	10	908	78	5976	86516	10000	32	552	112	5216	32	4942	32	1	5	5111	4	16	0	0	4	4	32405	147	80021	480	428	6	80000	160010	32383	32588	32334	32337	32360
240024	32515	244	2	0	0	0	6943	788	1	696	451	124	32228	762	526	1864	1553	1590	826	160042	80030	80000	80010	80000	400129	656550	0	1	28	49	29292	32482	32433	1213	1086	3	2396	160010	80020	160000	80020	80000	32402	38	1	1	80021	10	9	3	10	80000	10	80000	1	10	80976	32	466	4592	86047	794	13	941	90	5111	85554	10000	32	650	120	5230	32	4788	33	0	7	5020	4	16	0	0	7	6	32298	156	80028	479	419	1	80000	160010	32706	32518	32205	32344	32484
240024	32600	243	2	2	1	0	6871	794	1	712	425	240	32393	763	573	1916	1807	1510	778	160038	80034	80000	80010	80000	400120	659527	0	1	21	49	29397	32433	32672	1329	1003	3	2367	160010	80020	160000	80020	80000	32609	38	1	1	80021	10	9	8	10	80000	10	80000	1	10	80956	32	414	5244	84729	784	10	864	52	5525	86591	10000	32	696	126	6333	32	5006	33	0	9	5020	4	16	0	0	4	4	32613	145	80030	486	476	3	80000	160010	32310	32260	32580	32574	32660
240024	32551	241	2	0	0	0	6884	793	1	720	457	152	32673	831	548	1807	1761	1466	811	160039	80036	80000	80010	80000	400131	657898	1	1	17	49	29505	32336	32508	1314	1217	3	2367	160010	80020	160000	80020	80000	32389	38	1	1	80021	10	9	26	10	80000	10	80000	1	10	81000	34	431	4264	85420	794	15	900	74	6031	86589	10000	32	615	118	4975	32	4944	32	6	5	5020	4	16	0	0	8	4	32435	183	80032	514	478	2	80000	160010	32508	32406	32363	32224	32573
240024	32414	243	2	0	0	0	7215	772	1	720	456	100	32544	788	554	1581	1553	1338	784	160034	80036	80000	80010	80000	400108	676179	0	0	18	49	29382	32579	32476	1424	1124	3	2327	160010	80020	160000	80020	80000	32363	38	1	1	80021	10	9	1	10	80000	10	80000	1	10	80971	35	420	4838	85851	798	9	924	40	4974	86499	10000	32	605	127	5399	32	5210	32	0	3	5020	4	16	0	0	7	7	32492	168	80023	469	521	7	80000	160010	32420	32371	32753	32826	32317
240024	32877	243	2	2	0	0	7274	812	1	680	418	104	32500	792	499	1659	1811	1328	806	160036	80040	80000	80010	80000	400127	677864	0	1	17	49	29428	32558	32707	1459	1179	3	2651	160010	80020	160000	80020	80000	32426	38	1	1	80021	10	9	6	10	80000	10	80000	1	10	80944	20	415	4963	84747	763	11	934	24	5259	86668	10000	32	578	125	5583	32	4740	33	1	3	5020	6	16	0	0	4	4	32190	153	80026	501	498	1	80000	160010	32509	32578	32522	32403	32559
240024	32259	243	2	0	2	1	7604	767	1	728	448	140	32554	771	462	1600	2150	1274	823	160037	80033	80000	80010	80000	400117	679677	0	0	26	49	29276	32434	32447	1577	1042	3	2512	160010	80020	160000	80020	80000	32368	38	1	1	80021	10	9	10	10	80000	10	80000	1	10	80967	25	411	4723	85821	813	11	918	50	5736	85896	10000	32	682	126	5579	32	4850	32	0	4	5020	4	16	0	0	4	3	32769	144	80022	436	450	2	80000	160010	32495	32488	32333	32527	32451
240024	32532	243	2	2	0	0	7943	825	1	728	405	112	32564	788	564	1976	1618	1484	819	160032	80029	80000	80010	80000	400124	685388	0	1	27	49	29563	32632	32467	1407	1054	3	2684	160010	80020	160000	80020	80000	32581	38	1	1	80021	10	9	9	10	80000	10	80000	1	10	80970	13	413	5612	85752	845	12	881	66	5126	86113	10000	32	664	127	5915	32	4498	0	0	6	5020	4	16	0	0	4	3	32421	159	80030	548	434	7	80000	160010	32811	32429	32954	32447	32725
240024	32480	245	2	0	1	0	6877	810	1	744	427	100	32417	820	510	1814	1939	1262	849	160035	80037	80000	80010	80000	400181	668526	0	0	26	49	29504	32339	32472	1213	1032	3	2351	160010	80020	160000	80020	80000	32346	38	1	1	80021	10	9	14	10	80000	10	80000	1	10	80970	34	456	5375	85454	828	13	899	80	5530	86257	10000	32	692	122	5867	32	4776	31	3	7	5020	6	15	0	0	4	6	32302	156	80034	470	479	2	80000	160010	32449	32343	32486	32260	32543

LDP (pre-index, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations