Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

EON (register, asr, 32-bit)

Test 1: uops

Code:

  eon w0, w0, w1, asr #17
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100420351606110001735252000200010003257020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
100420351606110001735252000200010003257020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
100420351606110001735252000200010003257020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
100420351606110001735252000200010003257020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
100420351606110001735252000200010003257020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
100420351506110001735252000200010003257020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
100420351606110001735252000200010003257020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
10042035150103100017352520002000100032570203520351575318421000100020002035421110011000310731671117812000100020362036203620362036
100420351506110001735252000200010003257020352035157531842100010002000203542111001100000731671117812000100020362036203620362036
100420351606110001735252000200010003257020352035157531842100010002000203542111001100000731671117812000100020362036203620362036

Test 2: Latency 1->2

Code:

  eon w0, w0, w1, asr #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03181e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102042003515500611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000710159111979120000101002003620036200362003620036
102042003515500611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010003710159111979120000101002003620036200362003620036
102042003515500611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000710159111979120000101002003620036201722003620036
102042003515500611000019803252010020100101001853421491695520035200801842931870010100102002020020035421110201100991001010010010710159111979120000101002003620036200362003620036
102042003515500611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000710159111979120000101002003620036200362003620036
1020420035155006110000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100350710159111979120000101002003620036200362003620036
102042003515500611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000710159111979120000101002003620036200362003620036
102042003515500611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010003710159111979120000101002003620131200362008120036
102042003515510611000019803252010020100101001853421491695520035200351842931870010100102002054020035421110201100991001010010000710159111979120000101002003620036200362003620036
102042003515500611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010010710159111979120000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1002420035155000000023310000197432520010200101001018531049169552003520035184513187181001010020200202003542111002110910100101000000000640263221979220000100102003620036200362003620036
1002420035155000000014910000197432520010200101001018531049169552003520035184513187181001010020200202003542111002110910100101000000000640263221979220000100102003620036200362003620036
100242003515500000006110000197432520010200101001018531049169552003520035184513187181001010020200202003542111002110910100101000000000640263221979220000100102003620036200362003620036
1002420035155000000019410000197602520010200101001018531049169552003520035184513187181001010020200202003542111002110910100101000000000640263221979220000100102003620036200362003620036
100242008115500000006110000197432520010200101001018531049169552003520035184513187181001010020200202003542111002110910100101000000000640263221979220000100102003620036200362003620036
100242003515500000008210000197432520010200101001018531049169552003520035184513187181001010020200202003542111002110910100101000000000640263221979220000100102003620036200362003620036
100242003515500000006110000197432520010200101001018531049169552003520035184513187181001010020200202003542111002110910100101000000000640263221979220000100102003620036200362003620036
100242003515500000006110000197432520010200101001018531049169552003520035184513187181001010020200202003542111002110910100101000000000640263221979220000100102003620036200362003620036
100242003515500000006110000197432520010200101001018531049169552003520035184513187181001010020200202003542111002110910100101000000000640263221979220000100102003620036200362003620036
1002420035155000000067510000197432520010200101001018531049169552003520035184513187181001010020200202003542111002110910100101000000000640263221979220000100102003620036200362003620036

Test 3: Latency 1->3

Code:

  eon w0, w1, w0, asr #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1020420035155000012611000019803252010020100101001853421491695520035200351842931870010100102002020020035421110201100991001010010000000710159111979120000101002003620036200362003620036
102042003515500000611000019803252010020100101001853420491695520035200351842931870010100102002020020035421110201100991001010010000000710159111979120000101002003620036200362003620036
102042003515500000611000019803252010020100101001853420491695520035200351842931870010100102002020020035421110201100991001010010000000710159111979120000101002003620036200362003620036
102042003515500000611000019803252010020100101001853420491695520035200351842931870010100102002020020035421110201100991001010010000000710159111979120000101002003620036200362003620036
102042003515500000611000019803252010020100101001853420491695520035200351842931870010100102002020020035421110201100991001010010000030710159111979120000101002003620036200362003620036
1020420035155000001041000019803252010020100101001853420491695520035200351842931870010100102002020020035421110201100991001010010000230710159111979120000101002003620036200362003620036
10204200351550000211541000019803252010020100101001853420491695520035200351842931870010100102002020020035421110201100991001010010000130710159111979120000101002003620036200362003620036
10204200351560000272081000019803252010020100101001853420491695520035200351842931870010100102002020020035421110201100991001010010000160710159111979120000101002003620036200362003620036
1020420035155000001241000019803252010020100101001853420491695520035200351842931870010100102002020020035421110201100991001010010000230710159111979120000101002003620036200362003620036
102042003515600000611000019803252010020100101001853420491695520035200351842931870010100102002020020035421110201100991001010010000030710159111979120025101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f4c4d5051schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
10024200351550000061100001974320019252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010000000640463341979220000100102003620036200362003620036
10024200351550009023210000197430252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010000000640363341979220000100102003620036200362003620036
10024200351550016020110000197430252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010001000640363441979220000100102003620036200362003620036
1002420035155000006110000197430252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010000000640463431979220000100102003620036200362003620036
1002420035155000006110000197430252001020010100101853101491695520068200351845131871810010100202002020035421110021109101001010002030640463431979220000100102003620036200362003620036
1002420035156000006110000197430252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010001000640463341979220000100102003620036200362003620036
1002420035156000006110000197430252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010001000640463431979220000100102003620036200362003620036
1002420035155000006110000197430252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010004901440640363341979220000100102003620036200362003620036
1002420035155000006110000197430252001020010100101853101491695520035200351845131871810010100202002020035421110021109101001010008090640463441979220000100102003620036200362003620036
100242003515500012061100001974302520010200101001018531014916955200352003518451318718100101002020020200354211100211091010010100070120640363441979220000100102003620036200362003620036

Test 4: throughput

Count: 8

Code:

  eon w0, w8, w9, asr #17
  eon w1, w8, w9, asr #17
  eon w2, w8, w9, asr #17
  eon w3, w8, w9, asr #17
  eon w4, w8, w9, asr #17
  eon w5, w8, w9, asr #17
  eon w6, w8, w9, asr #17
  eon w7, w8, w9, asr #17
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

retire uop (01)cycle (02)03mmu table walk data (08)191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)6067696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
802042676821500117606180000260942516010016010080100164318004923645267252672516615316677801008020016020026725391180201100991008010010000000051103221126717160000801002672626726267262672626726
802042672521500210028580000260942516010016010080100164318004923645267252672516615316677801008020016020026725391180201100991008010010000000051101221126717160000801002672626726267262672626726
80204267252070000618000026094251601001601008010016431800492364526725267251661531667780100802001602002672539118020110099100801001000007830051101221126717160000801002672626726267262672626726
802042672520700006180000260942516010016010080100164318004923645267252672516615316677801008020016020026725391180201100991008010010000000051101221126717160000801002672626726267262672626726
802042672520700006180000260942516010016010080100164318004923645267252672516615316677801008020016020026725391180201100991008010010000000051101221126717160000801002672626788267262672626726
802042672521500006180000260942516010016010080100164318004923645267252672516615316677801008020016020026725391180201100991008010010000000051101221126717160000801002672626726267262672626726
802042672521500006180000260302516010016010080100164318004923645267252672516615316677801008020016020026725391180201100991008010010000016730051101221126717160000801002672626726267262672626726
802042672521400006180000260942516010016010080498184014104923645267252672516615316677801008020016020026725391180201100991008010010000000051831221126717160000801002672626726267262672626845
80204267252070040806180000260942516010016010080100164318004923645267252672516615316677801008020016020026725391180201100991008010010000000051101221126717160000801002672626726267262672626726
80204267252070051906180000260942516010016010080100164318004923645267252672516615316677801008020016020026725391180201100991008010010000000051102221126717160000801002672626726267262672626726

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)5f60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acc2c9cfd5map dispatch bubble (d6)d9ddfetch restart (de)e0? int output thing (e9)ea? int retires (ef)f5f6f7f8fd
80024267352070000010380000212802516001016001080010163142004923631267112671116623316685800108002016002026711391180021109108001010000000005020522047267041600000800102677126712267122688626712
800242671120700012013180000212802516001016001080010163142004923631267112671116623316685800108002016002026711391180021109108001010000013005020422043267041600000800102671226712267122671226712
8002426711207000006180000212802516001016001080010163142004923631267112671116623316685800108002016002026711391180021109108001010000000005020422074267041600000800102671226712267122671226712
80024267112150001208980000212802516001016001080010163142004923631267692671116623316685800108002016002026711391180021109108001010000010005020322067267041600000800102671226712267122671226712
800242671120700012013180000212802516001016001080010163142014923631267112671116623316685800108002016002026711391180021109108001010000003005020422034267041600000800102671226712267122671226712
800242671120700012013280000212802516001016001080010163142004923631267112671116623316685800108002016002026711391180021109108001010000003005020622043267041600000800102671226712267122671226712
80024267112070000071980000212802516001016001080010163142004923631267112671116623316685800108002016002026711391180021109108001010000013005020422044267041600000800102671226712267122671226712
80024267112070000010380000212802516001016001080010163142004923631267112671116623316685800108002016002026711391180021109108001010000013005020722046267041600000800102671226712267122671226712
800242671121500012010380000207819516001016001080010163142014923631267112671116623316685800108002016002026711391180021109108001010000010005020622077267041600000800102671226712267122671226712
8002426711207000006180000212802516001016001080010163142004923631267112671116623316685800108002016002026711391180021109108001010000000005020722047267041600000800102671226712267122671226712