Firestorm: EXTR (register, 64-bit) measurements

Code:

  extr x0, x0, x1, 13

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
2004	1036	8	0	0	46	25	2000	2000	2000	11000	0	1036	1036	739	3	768	2000	2000	3000	1036	84	1	1	1001	1000	0	0	73	1	17	1	1	1033	2000	2000	1037	1037	1037	1037	1037
2004	1036	8	0	0	46	25	2000	2000	2000	11000	0	1036	1036	739	3	768	2000	2000	3000	1036	84	1	1	1001	1000	0	0	73	1	17	1	1	1033	2000	2000	1037	1037	1037	1037	1037
2004	1036	8	0	0	46	25	2000	2000	2000	11000	0	1036	1036	739	3	768	2000	2000	3000	1036	84	1	1	1001	1000	0	0	73	1	17	1	1	1033	2000	2000	1037	1037	1037	1037	1037
2004	1036	8	0	0	46	25	2000	2000	2000	11000	0	1036	1036	739	3	768	2000	2000	3000	1036	84	1	1	1001	1000	0	0	73	1	17	1	1	1033	2000	2000	1037	1037	1037	1037	1037
2004	1036	8	0	0	46	25	2000	2000	2000	11000	0	1036	1036	739	3	768	2000	2000	3000	1036	84	1	1	1001	1000	0	0	73	1	17	1	1	1033	2000	2000	1037	1037	1037	1037	1037
2004	1036	7	0	0	46	25	2000	2000	2000	11000	0	1036	1036	739	3	768	2000	2000	3000	1036	84	1	1	1001	1000	0	0	73	1	17	1	1	1033	2000	2000	1037	1037	1037	1037	1037
2004	1036	7	0	0	46	25	2000	2000	2000	11000	0	1036	1036	739	3	768	2000	2000	3000	1036	84	1	1	1001	1000	0	0	73	1	17	1	1	1033	2000	2000	1037	1037	1037	1037	1037
2004	1036	7	1	264	46	25	2000	2000	2000	11000	0	1036	1036	739	3	768	2000	2000	3000	1036	84	1	1	1001	1000	0	0	73	1	17	1	1	1033	2000	2000	1037	1037	1037	1037	1037
2004	1036	7	0	0	46	25	2000	2000	2000	11000	0	1036	1036	739	3	768	2000	2000	3000	1036	84	1	1	1001	1000	0	0	73	1	17	1	1	1033	2000	2000	1037	1037	1037	1037	1037
2004	1036	8	0	15	46	25	2000	2000	2000	11000	0	1036	1036	739	3	768	2000	2000	3000	1036	84	1	1	1001	1000	0	0	73	1	17	1	1	1033	2000	2000	1037	1037	1037	1037	1037

Test 2: Latency 1->2

Code:

  extr x0, x0, x1, 13

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0036

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	10045	75	0	0	0	47	25	20100	20100	20100	110500	1	49	6956	10036	10083	7464	3	7494	20100	20200	30200	10036	84	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	16	1	1	10033	20054	20100	10037	10037	10037	10037	10037
20204	10036	75	0	57	0	47	25	20100	20100	20100	110500	1	49	6956	10036	10036	7464	3	7494	20100	20200	30200	10036	84	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	16	1	1	10033	20000	20100	10037	10037	10037	10037	10037
20204	10036	75	0	54	0	47	25	20100	20100	20100	110500	1	49	6956	10036	10036	7464	3	7494	20100	20266	30200	10036	84	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	16	2	1	10033	20000	20100	10037	10037	10037	10037	10037
20204	10036	75	0	60	0	47	25	20100	20100	20100	110500	1	49	6956	10036	10036	7464	3	7494	20100	20200	30200	10036	84	1	1	10201	100	99	100	10100	100	0	2	0	0	0	0	710	1	16	1	1	10033	20000	20100	10037	10037	10037	10037	10037
20204	10036	75	0	54	0	47	25	20100	20100	20100	110500	0	49	6956	10036	10036	7464	3	7494	20100	20200	30200	10036	84	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	16	1	1	10033	20000	20100	10037	10037	10037	10037	10037
20204	10036	75	0	60	0	47	25	20100	20100	20100	110500	0	49	6956	10036	10036	7464	3	7494	20100	20200	30200	10036	84	1	1	10201	100	99	100	10100	100	0	0	0	0	2	0	710	1	16	1	1	10033	20054	20100	10085	10037	10037	10084	10037
20204	10036	75	0	6	0	47	25	20100	20154	20100	110500	1	49	6956	10036	10036	7464	3	7494	20100	20200	30200	10036	84	2	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	16	1	1	10033	20000	20100	10037	10037	10037	10037	10037
20204	10036	75	0	9	0	47	25	20100	20100	20100	110500	1	49	6956	10036	10036	7464	3	7494	20100	20200	30200	10036	84	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	16	1	1	10033	20000	20100	10037	10037	10037	10037	10037
20204	10036	75	0	39	0	1919	25	20100	20100	20100	110500	1	49	6956	10036	10036	7464	3	7494	20100	20200	30200	10036	84	1	1	10201	100	99	100	10100	100	0	0	0	0	0	0	710	1	16	1	1	10033	20000	20100	10037	10037	10037	10037	10037
20204	10036	75	0	0	0	47	25	20100	20100	20100	110500	1	49	6956	10036	10036	7464	3	7494	20100	20200	30200	10036	84	1	1	10201	100	99	100	10100	100	0	0	0	1	0	0	710	1	16	1	1	10033	20000	20100	10037	10037	10037	10037	10037

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0036

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	10036	75	0	0	0	255	563	25	20010	20010	20010	110050	49	6956	10036	10036	7486	3	7515	20010	20020	30020	10036	84	1	1	10021	10	9	10	10010	10	0	0	0	0	640	5	17	6	7	10033	20000	20010	10037	10037	10037	10037	10037
20024	10036	75	0	0	0	294	46	25	20010	20010	20010	110050	49	6956	10036	10036	7486	3	7515	20010	20020	30020	10036	84	1	1	10021	10	9	10	10010	10	0	0	0	0	640	6	17	6	5	10033	20000	20010	10037	10037	10037	10037	10037
20024	10036	75	0	0	0	306	46	25	20010	20010	20010	110050	49	6956	10036	10036	7501	3	7515	20010	20020	30020	10036	84	1	1	10021	10	9	10	10010	10	0	0	0	0	640	7	17	6	7	10033	20000	20010	10037	10037	10037	10037	10037
20024	10036	75	0	1	0	306	46	25	20010	20010	20010	110050	49	7052	10036	10036	7486	3	7515	20010	20020	30020	10036	84	1	1	10021	10	9	10	10010	10	0	0	0	0	640	6	17	6	6	10033	20000	20010	10037	10037	10037	10037	10037
20024	10036	75	0	0	0	45	88	25	20010	20010	20010	110050	49	6956	10036	10036	7486	3	7515	20010	20020	30020	10036	84	1	1	10021	10	9	10	10010	10	0	0	0	0	640	6	17	6	6	10033	20000	20010	10037	10037	10037	10037	10037
20024	10036	75	0	0	0	138	46	25	20010	20010	20010	110050	49	6956	10036	10036	7486	3	7515	20010	20020	30020	10036	84	1	1	10021	10	9	10	10010	10	0	0	0	0	640	7	17	7	7	10033	20000	20010	10037	10037	10037	10037	10037
20024	10036	75	0	0	0	432	46	25	20010	20010	20010	110050	49	6956	10036	10036	7486	3	7515	20010	20020	30020	10036	84	1	1	10021	10	9	10	10010	10	0	0	0	0	640	6	17	7	6	10033	20000	20010	10037	10037	10037	10037	10037
20024	10036	75	0	0	0	417	46	25	20010	20010	20010	110050	49	6956	10036	10036	7486	3	7515	20010	20020	30020	10036	84	1	1	10021	10	9	10	10010	10	0	0	0	0	640	7	17	7	7	10033	20000	20010	10037	10037	10037	10037	10037
20024	10036	75	0	0	0	12	46	25	20010	20010	20010	110050	49	6956	10036	10036	7486	3	7515	20010	20020	30020	10036	84	1	1	10021	10	9	10	10010	10	0	0	0	0	640	7	17	7	6	10033	20000	20010	10037	10037	10037	10037	10037
20024	10036	75	0	0	1	45	46	25	20010	20010	20010	110050	49	6956	10036	10036	7486	3	7515	20010	20020	30020	10036	84	1	1	10021	10	9	10	10010	10	0	0	0	0	640	7	17	7	6	10033	20000	20010	10037	10037	10037	10037	10037

Test 3: Latency 1->3

Code:

  extr x0, x1, x0, 13

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	24	61	9951	25	20100	20100	20100	1264318	0	49	16955	20035	20035	17406	3	17493	20100	20200	30200	20035	104	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	19993	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	9951	25	20100	20100	20100	1264318	0	49	16955	20035	20035	17406	3	17493	20100	20200	30200	20035	104	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	19993	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	103	9951	25	20100	20100	20100	1264318	0	49	16955	20035	20035	17406	3	17493	20100	20200	30200	20035	104	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	19993	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	9951	25	20100	20100	20100	1264318	0	49	16955	20035	20035	17406	3	17493	20100	20200	30200	20035	104	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	19993	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	9951	25	20100	20100	20100	1264318	0	49	16955	20035	20035	17406	3	17493	20100	20200	30200	20035	104	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	19993	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	9951	25	20100	20100	20100	1264318	0	49	16955	20035	20035	17406	3	17493	20100	20200	30200	20035	104	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	19993	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	9951	25	20100	20100	20100	1264318	0	49	16955	20035	20035	17406	3	17493	20100	20200	30200	20035	104	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	19993	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	9951	25	20100	20100	20100	1264318	0	49	16955	20035	20035	17406	3	17493	20100	20200	30200	20035	104	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	19993	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	9951	25	20100	20100	20100	1264318	0	49	16955	20035	20035	17406	3	17493	20100	20200	30200	20035	104	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	19993	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	0	61	9951	25	20100	20100	20100	1264318	0	49	16955	20035	20035	17406	3	17493	20100	20200	30200	20035	104	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	19993	20000	20100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	15	61	9953	25	20010	20010	20010	1268655	49	16955	20035	20035	17424	3	17515	20010	20020	30020	20035	104	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	16	2	2	19991	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	103	9953	25	20010	20010	20010	1268655	49	16955	20035	20035	17424	3	17515	20010	20020	30020	20035	104	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	16	2	2	19991	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	18	61	9953	25	20010	20010	20010	1268655	49	16955	20035	20035	17424	3	17515	20010	20020	30020	20035	104	1	1	10021	10	9	10	10010	10	0	1	0	0	0	640	2	16	2	2	19991	20000	20010	20036	20036	20083	20036	20036
20024	20080	150	1	9	61	9953	25	20010	20010	20010	1268655	49	16955	20035	20035	17424	7	17515	20010	20020	30020	20035	104	1	1	10021	10	9	10	10010	10	2	1	0	0	0	640	2	16	2	2	19991	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	264	61	9953	25	20010	20010	20010	1268655	49	16955	20035	20035	17424	13	17515	20010	20020	30020	20035	104	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	16	2	2	19991	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	9953	25	20010	20010	20010	1268655	49	16955	20035	20035	17424	3	17515	20010	20020	30020	20035	104	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	16	2	2	19991	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	36	61	9953	25	20010	20010	20010	1268655	49	16955	20035	20035	17424	3	17515	20010	20020	30020	20035	104	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	16	2	2	19991	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	18	61	9953	46	20032	20010	20010	1268655	49	16955	20035	20035	17424	3	17515	20010	20020	30020	20035	104	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	16	2	2	19991	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	9953	25	20010	20010	20010	1268655	49	16955	20035	20035	17424	3	17515	20010	20020	30020	20035	104	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	16	2	2	19991	20000	20010	20036	20036	20036	20036	20036
20024	20035	149	0	21	61	9953	25	20010	20010	20010	1268655	49	16955	20035	20035	17424	3	17515	20010	20020	30020	20035	104	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	16	2	2	19991	20000	20010	20036	20036	20036	20036	20036

Test 4: throughput

Count: 8

Code:

  extr x0, x8, x9, 13
  extr x1, x8, x9, 13
  extr x2, x8, x9, 13
  extr x3, x8, x9, 13
  extr x4, x8, x9, 13
  extr x5, x8, x9, 13
  extr x6, x8, x9, 13
  extr x7, x8, x9, 13

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
160204	80040	600	0	712	25	160100	160100	160100	880500	1	49	76956	0	80036	80036	59964	3	59994	160100	160200	240200	80036	84	1	1	80201	100	99	100	80100	100	0	1	0	0	5136	2	16	1	1	80033	160000	160100	80037	80037	80037	80037	80037
160204	80036	599	0	47	25	160100	160100	160100	880500	1	49	76956	0	80036	80036	59964	3	59994	160100	160200	240200	80036	84	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	1	16	1	1	80033	160000	160100	80037	80037	80037	80037	80037
160204	80036	600	0	47	25	160100	160100	160100	880500	0	49	76956	0	80036	80036	59964	3	59994	160100	160200	240200	80036	84	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	1	16	1	1	80033	160000	160100	80037	80037	80037	80037	80037
160204	80036	599	0	47	25	160100	160100	160100	921117	1	49	76956	3	80036	80036	59964	3	59994	160100	160200	240200	80036	84	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	1	16	1	1	80033	160000	160100	80037	80037	80037	80037	80037
160204	80036	600	0	712	25	160100	160100	160100	880500	1	49	76956	0	80036	80036	59964	3	59994	160100	160200	240200	80036	84	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	1	16	1	1	80033	160000	160100	80037	80037	80037	80037	80037
160204	80036	600	0	522	25	160100	160100	160100	880500	1	49	76956	0	80036	80036	59964	3	59994	160100	160200	240200	80036	84	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	1	16	1	1	80033	160000	160100	80037	80037	80037	80037	80037
160204	80036	599	0	47	25	160100	160100	160100	880500	1	49	76956	0	80036	80036	59964	3	59994	160100	160200	240200	80036	84	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	1	16	1	1	80033	160000	160100	80037	80037	80037	80037	80037
160204	80036	599	0	68	25	160100	160100	160100	880500	1	49	76956	0	80036	80036	59964	3	59994	160100	160200	240200	80036	84	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	1	16	1	1	80033	160000	160100	80037	80037	80037	80037	80037
160204	80036	599	12	47	25	160100	160100	160100	880500	1	49	76956	0	80036	80036	59964	3	59994	160100	160200	240200	80036	84	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	1	16	1	1	80033	160000	160100	80037	80037	80037	80037	80037
160204	80036	599	0	47	25	160100	160100	160100	880500	1	49	76956	0	80036	80036	59964	3	59994	160100	160200	240200	80036	84	1	1	80201	100	99	100	80100	100	0	0	0	0	5110	1	16	1	1	80033	160000	160100	80037	80037	80037	80037	80037

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	int prf full (71)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
160024	80038	599	0	46	25	160010	160010	160010	880050	1	49	76956	80036	80036	59986	0	3	60015	160010	160020	240020	80036	84	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	1	17	1	1	80033	160000	160010	80037	80037	80037	80037	80037
160024	80036	599	0	46	25	160010	160010	160010	880050	1	49	76956	80036	80036	59986	0	3	60015	160010	160020	240020	80036	84	1	1	80021	10	9	10	80010	10	0	0	0	1	0	5020	1	17	1	1	80033	160000	160010	80037	80037	80037	80037	80037
160024	80073	599	0	46	25	160010	160010	160010	880050	1	49	76956	80036	80036	59986	0	3	60015	160010	160020	240020	80036	84	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	1	17	1	1	80033	160000	160010	80037	80037	80037	80037	80037
160024	80036	600	0	46	25	160010	160010	160010	880050	1	49	76956	80036	80036	60008	0	3	60015	160010	160020	240020	80036	84	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	1	17	1	1	80033	160000	160010	80037	80037	80037	80037	80078
160024	80036	600	0	46	25	160010	160010	160010	880050	1	49	76956	80079	80036	59986	0	3	60015	160010	160020	240020	80079	84	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	1	17	1	2	80033	160000	160010	80037	80037	80037	80037	80037
160024	80036	599	0	46	25	160010	160010	160010	880050	1	49	76956	80036	80036	59986	0	3	60015	160010	160020	240020	80036	84	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	1	17	1	1	80033	160000	160010	80037	80037	80037	80037	80037
160024	80036	599	0	829	25	160010	160010	160010	880050	1	49	76956	80036	80036	59986	0	3	60015	160010	160020	240020	80036	84	1	1	80021	10	9	10	80010	10	0	3	0	0	0	5020	1	17	1	1	80033	160000	160010	80037	80037	80037	80037	80037
160024	80036	599	0	789	25	160010	160010	160010	880050	1	49	76956	80036	80036	59986	0	3	60015	160010	160020	240020	80036	84	2	1	80021	10	9	10	80010	10	0	524	2	0	0	5020	1	17	1	1	80033	160000	160010	80037	80037	80037	80037	80037
160024	80036	599	0	46	25	160010	160010	160010	880050	1	49	76956	80036	80036	59986	0	3	60015	160010	160020	240020	80036	84	1	1	80021	10	9	10	80010	10	1	0	0	0	0	5020	1	53	1	1	80033	160216	160010	80037	80037	80037	80037	80037
160024	80036	599	0	46	25	160010	160010	160010	880050	1	49	76956	80036	80036	59986	0	3	60015	160010	160020	240020	80036	84	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	1	17	1	1	80033	160000	160010	80037	80037	80037	80037	80037

EXTR (register, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations