Firestorm: PRFM (register, PLIL3STRM) measurements

Code:

  prfm plil3strm, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	92	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1004	1469	11	43	35	45	2703	1436	770	25	1000	1000	1000	63520	1468	1491	1170	3	1338	1000	1000	1000	1442	1456	1	1	1001	4	2496	2560	3561	2771	2553	1000	73	1	16	1	1	1386	1000	1445	1467	1466	1480	1447
1004	1487	11	43	36	44	2711	1445	767	25	1000	1000	1000	63091	1469	1458	1175	3	1338	1000	1000	1000	1454	1452	1	1	1001	5	2520	2517	3585	2766	2522	1000	73	1	16	1	1	1374	1000	1487	1472	1480	1476	1460
1004	1473	11	45	38	44	2747	1429	747	25	1000	1000	1000	63464	1461	1452	1180	3	1312	1000	1000	1000	1444	1453	1	1	1001	10	2607	2535	3560	2742	2537	1000	73	1	16	1	1	1391	1000	1460	1468	1448	1484	1468
1004	1451	11	45	35	43	2754	1434	777	25	1000	1000	1000	63203	1456	1474	1177	3	1302	1000	1000	1000	1457	1473	1	1	1001	22	2547	2587	3543	2697	2561	1000	73	1	16	1	1	1381	1000	1472	1487	1471	1469	1472
1004	1455	11	45	34	44	2749	1434	787	25	1000	1000	1000	64106	1457	1468	1179	3	1311	1000	1000	1000	1467	1460	1	1	1001	12	2536	2526	3568	2708	2521	1000	73	1	16	1	1	1367	1000	1476	1478	1477	1488	1456
1004	1483	11	44	36	44	2758	1443	781	25	1000	1000	1000	62556	1474	1457	1162	3	1322	1000	1000	1000	1466	1468	1	1	1001	0	2520	2561	3585	2740	2529	1000	73	1	16	1	1	1382	1000	1470	1469	1486	1488	1458
1004	1442	11	44	34	44	2753	1461	773	25	1000	1000	1000	63476	1447	1477	1183	3	1315	1000	1000	1000	1471	1484	1	1	1001	5	2533	2564	3595	2755	2515	1000	73	1	16	1	1	1376	1000	1460	1465	1461	1452	1472
1004	1472	11	45	37	45	2721	1471	774	25	1000	1000	1000	63277	1478	1472	1179	3	1327	1000	1000	1000	1472	1454	1	1	1001	0	2553	2541	3586	2753	2565	1000	73	1	16	1	1	1392	1000	1456	1476	1453	1455	1483
1004	1465	11	44	35	44	2734	1473	766	25	1000	1000	1000	63298	1464	1469	1164	3	1359	1000	1000	1000	1442	1461	1	1	1001	4	2571	2564	3539	2734	2585	1000	73	1	16	1	1	1378	1000	1456	1459	1462	1452	1456
1004	1458	11	45	37	45	2756	1431	777	25	1000	1000	1000	63487	1473	1451	1186	3	1346	1000	1000	1000	1470	1468	1	1	1001	6	2543	2595	3565	2721	2556	1000	73	1	16	1	1	1375	1000	1488	1454	1456	1465	1468

Test 2: throughput

Code:

  prfm plil3strm, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5727

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	15697	119	350	176	352	24505	15732	9787	25	20175	10214	10000	10104	10001	133382	743934	1	31	49	12621	0	15619	15837	13016	6	13147	20100	10208	10012	10208	10004	15814	144	1	1	20201	100	99	2391	100	10100	100	22904	22830	32756	0	24397	22803	10000	0	1	1	1	1318	0	16	0	0	15698	10097	10000	10100	15898	15865	15749	15718	15727
20204	15667	118	354	186	349	24527	15615	9849	25	20187	10224	10000	10108	10001	132234	738435	1	34	49	12740	0	15769	15660	12942	3	13251	20100	10200	10000	10200	10000	15682	140	1	1	20201	100	99	2333	100	10100	100	22672	22896	33100	0	24405	23180	10000	0	0	0	0	1310	1	17	1	1	15643	10087	10000	10100	15822	15706	15691	15724	15770
20204	15749	118	350	182	351	24478	15767	9974	25	20208	10175	10000	10100	10000	134031	742326	0	34	49	12703	0	15784	15858	13036	3	13157	20100	10200	10000	10200	10000	15669	138	1	1	20201	100	99	2332	100	10100	100	22871	22739	32883	0	24429	22805	10000	0	0	0	0	1310	1	16	1	1	15596	10111	10000	10100	15673	15807	15620	15582	15777
20204	15589	117	349	186	352	24374	15686	9808	25	20220	10181	10000	10100	10000	131974	737936	1	33	49	12744	0	15749	15727	13095	3	13028	20100	10200	10000	10200	10000	15623	147	1	1	20201	100	99	2496	100	10100	100	22859	22844	32858	0	24493	22828	10000	0	0	0	0	1310	1	17	1	1	15608	10105	10000	10100	15955	15829	15895	15795	15678
20204	15752	119	353	185	356	24481	15754	9749	25	20229	10172	10000	10100	10000	132709	740226	1	31	49	12624	0	15763	15710	13077	3	13096	20100	10200	10000	10200	10000	15605	148	1	1	20201	100	99	2355	100	10100	100	22921	22967	32887	0	24482	23126	10000	0	0	0	0	1310	1	16	1	1	15663	10108	10000	10100	15686	15907	15742	15667	15843
20204	15681	118	352	184	354	24395	15697	9682	25	20226	10205	10000	10100	10000	132353	737226	1	38	49	12774	0	15716	15803	12944	3	13200	20100	10200	10000	10200	10000	15637	138	1	1	20201	100	99	2389	100	10100	100	22783	22958	32838	0	24692	22873	10000	0	0	0	0	1310	1	16	1	1	15571	10111	10000	10100	15884	15807	15668	15730	15803
20204	15600	117	351	191	354	24508	15701	9575	25	20226	10211	10000	10100	10000	132827	736533	1	35	49	12563	0	15588	15625	13088	3	13123	20100	10200	10000	10200	10000	15607	139	1	1	20201	100	99	2450	100	10100	100	22895	22849	32773	0	24583	22753	10000	0	0	0	0	1310	1	17	1	1	15709	10129	10000	10100	15597	15783	15793	15784	15714
20204	15730	118	352	186	352	24621	15739	9809	25	20229	10211	10000	10100	10000	133052	731905	1	27	49	12613	0	15708	15831	13058	3	13110	20100	10200	10000	10200	10000	15730	147	1	1	20201	100	99	2420	100	10100	100	22900	22697	32872	0	24453	22892	10000	0	0	0	0	1310	1	16	1	1	15703	10132	10000	10100	15719	15813	15728	15648	15778
20204	15637	117	350	187	348	24489	15693	9736	25	20221	10196	10000	10100	10000	132802	738804	1	32	49	12557	0	15811	15799	12987	3	13151	20100	10200	10000	10200	10000	15668	145	1	1	20201	100	99	2440	100	10100	100	22892	22731	32793	0	24657	22674	10000	0	0	0	0	1310	1	16	1	1	15551	10090	10000	10100	15676	15661	15715	15584	15728
20204	15734	118	348	189	351	24524	15838	9822	25	20232	10184	10000	10100	10000	131754	737007	1	39	49	12662	0	15752	15801	12902	3	13085	20100	10200	10000	10200	10000	15751	150	1	1	20201	100	99	2449	100	10100	100	22823	22734	32901	0	24500	22783	10000	0	0	0	0	1310	1	16	1	1	15531	10156	10000	10100	15761	15661	15736	15765	15775

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5601

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	67	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	15601	116	367	198	370	24816	15594	9664	25	20124	10169	10000	10010	10000	130906	729778	0	39	49	12632	15557	15701	12970	3	13036	20010	10020	10000	10020	10000	15603	145	1	1	20021	10	9	2054	10	10010	10	23344	23179	33094	0	24813	22954	10000	0	1270	1	16	1	1	15285	10138	10000	10010	15700	15730	15552	15663	15699
20024	15651	117	369	189	368	25050	15682	9742	25	20130	10142	10000	10010	10000	131553	725908	0	53	49	12560	15548	15656	12919	3	13129	20010	10020	10000	10020	10000	15607	143	1	1	20021	10	9	2307	10	10010	10	22957	23206	33220	0	24857	23060	10000	0	1270	1	16	1	1	15528	10138	10000	10010	15511	15662	15511	16058	15609
20024	15584	115	362	196	375	24703	15605	9705	25	20139	10142	10000	10010	10000	131932	737882	0	46	49	12538	15490	15687	12872	3	13001	20010	10020	10000	10020	10000	15536	153	1	1	20021	10	9	2218	10	10010	10	23181	23051	33111	0	24812	23130	10000	0	1270	1	16	1	1	15514	10144	10000	10010	15587	15644	15644	15590	15586
20024	15501	117	372	182	372	24966	15630	9637	25	20160	10124	10000	10010	10000	131704	726590	1	50	49	12467	15574	15638	12797	3	13273	20010	10020	10000	10020	10000	15675	143	1	1	20021	10	9	2297	10	10010	10	23095	23129	33309	2	24901	23302	10000	0	1270	1	16	1	1	15441	10150	10000	10010	15762	15513	15520	15635	15623
20024	15642	117	368	193	366	24931	15609	9465	25	20133	10127	10000	10010	10000	131088	734362	0	44	49	12441	15526	15596	13001	3	12934	20010	10020	10000	10020	10000	15695	155	1	1	20021	10	9	2199	10	10010	10	23167	23311	33019	0	24824	23070	10000	0	1270	1	16	1	1	15364	10132	10000	10010	15559	16229	15624	15372	15650
20024	15541	116	364	181	370	24688	15585	9756	25	20136	10106	10000	10010	10000	130074	730121	1	40	49	12583	15552	15518	12896	3	13024	20010	10020	10000	10020	10000	15479	150	1	1	20021	10	9	2171	10	10010	10	23069	23349	33058	0	24799	22812	10000	0	1270	1	16	1	1	15464	10132	10000	10010	15664	15593	15583	15630	15541
20024	15626	118	370	191	375	24904	15602	9625	25	20166	10175	10000	10010	10000	131680	725886	0	42	49	12536	15443	15646	12940	3	13080	20010	10020	10000	10020	10000	15497	151	1	1	20021	10	9	2265	10	10010	10	23349	23378	33156	0	24695	23112	10000	0	1270	1	16	1	1	15567	10111	10000	10010	15521	15583	15451	15533	15661
20024	15599	115	373	191	369	24930	15634	9626	25	20151	10157	10000	10010	10000	130844	729110	0	31	49	12527	15629	15571	12869	3	13047	20010	10020	10000	10020	10000	15463	154	1	1	20021	10	9	2233	10	10010	10	23215	23127	33219	0	24932	23178	10000	0	1270	1	16	1	1	15460	10129	10000	10010	15677	15761	15559	15586	15540
20024	15758	116	371	187	364	24826	15702	9641	25	20103	10160	10000	10010	10000	136623	730470	1	42	49	12489	15748	15472	12911	3	13098	20010	10020	10000	10020	10000	15641	141	1	1	20021	10	9	2179	10	10010	10	23279	23312	33129	1	24585	23174	10000	0	1270	1	16	1	1	15597	10117	10000	10010	15543	15614	15672	15658	15535
20024	15533	117	376	189	378	24874	15584	9695	25	20175	10133	10000	10010	10000	130283	729631	0	40	49	12582	15606	15506	12871	3	13024	20010	10020	10000	10020	10000	15580	152	1	1	20021	10	9	2170	10	10010	10	23098	23022	33399	0	24879	23186	10000	0	1271	1	16	1	1	15443	10144	10000	10010	15619	15630	15675	15562	15641

Test 3: throughput

Code:

  prfm plil3strm, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.5560

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	bb	l1d tlb miss nonspec (c1)	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10204	15646	116	1	296	150	1	294	23887	0	15429	9656	25	10100	100	10000	100	10000	500	727306	1	49	12521	15639	15428	14173	6	14272	10109	200	10008	200	10016	15491	12187	1	1	10201	100	99	2660	100	100	100	22298	22286	32304	0	0	23998	22299	10000	1	1	1	717	1	16	1	5	15374	10000	100	15609	15581	15544	15542	15532
10204	15529	116	1	298	148	1	298	23947	0	15602	9650	25	10100	100	10000	100	10000	500	728374	0	49	12554	15565	15522	14144	6	14267	10107	200	10008	200	10008	15601	15672	1	1	10201	100	99	2692	100	100	100	22287	22291	32296	0	0	24056	22292	10000	1	1	1	723	4	24	4	4	15386	10000	100	15585	15649	15527	15600	15618
10204	15481	117	1	299	148	1	294	23994	2	15427	9593	25	10100	100	10000	100	10000	500	723082	1	49	12457	15571	15631	14160	6	14200	10100	200	10000	200	10000	15544	12271	1	1	10201	100	99	2718	100	100	100	22299	22238	32306	0	0	23995	22284	10000	1	1	1	723	4	24	4	4	15506	10000	100	15456	15536	15577	15627	15574
10204	15586	116	1	292	146	1	293	23967	2	15579	9610	25	10100	100	10000	100	10000	500	727716	1	49	12463	15555	15582	14118	6	14257	10100	200	10000	200	10000	15579	12330	1	1	10201	100	99	2632	100	100	100	22411	22195	32331	0	0	23937	22303	10000	1	1	1	723	4	24	4	4	15436	10000	100	15547	15551	15569	15530	15626
10204	15565	116	1	296	147	1	299	23965	2	15571	9584	25	10100	100	10000	100	10000	500	728759	1	49	12515	15540	15618	14140	6	14196	10100	200	10000	200	10000	15493	12226	1	1	10201	100	99	2697	100	100	100	22310	22272	32300	0	1	24010	22328	10000	1	1	1	723	4	24	4	4	15437	10000	100	15478	15485	15528	15605	15613
10204	15560	117	1	296	147	1	295	24003	1	15491	9710	25	10100	100	10000	100	10000	500	726584	0	49	12475	15520	15595	14188	6	14237	10100	200	10000	200	10000	15530	12297	1	1	10201	100	99	2673	100	100	100	22359	22300	32349	0	4	23966	22277	10000	1	1	1	724	4	24	5	4	15403	10000	100	15584	15491	15589	16176	15590
10204	15557	116	1	295	149	0	294	24017	2	15579	9711	25	10100	100	10000	100	10000	500	729744	0	49	12534	15552	15580	14233	6	14295	10100	200	10000	200	10000	15489	12316	1	1	10201	100	99	2642	100	100	100	22283	22204	32264	0	0	24070	22285	10000	1	1	1	723	4	24	4	4	15499	10000	100	15590	15580	15506	15572	15495
10204	15502	116	1	294	148	1	295	24058	1	15566	9604	25	10100	100	10000	100	10000	500	730877	0	49	12490	15588	15508	14120	6	14295	10100	200	10000	200	10000	15529	12180	1	1	10201	100	99	2726	100	100	100	22327	22262	32307	0	0	23976	22249	10000	1	1	1	727	4	24	4	8	15402	10000	100	15674	15593	15590	15536	15487
10204	15562	116	1	296	147	1	295	23981	1	15667	9569	25	10100	100	10000	100	10000	500	726702	0	49	12499	15576	15565	14140	6	14274	10100	200	10000	200	10000	15529	12256	1	1	10201	100	99	2730	100	100	100	22325	22249	32244	0	0	23972	22270	10000	1	1	1	723	4	24	4	4	15417	10000	100	15593	15633	15629	15585	15581
10204	15596	116	0	296	148	0	296	23995	1	15546	9664	25	10100	100	10000	100	10000	500	731498	0	49	12551	15541	15563	14047	6	14264	10100	200	10000	200	10000	15549	12253	1	1	10201	100	99	2709	100	100	100	22280	22312	32289	0	6	23982	22312	10000	1	1	1	722	4	24	4	4	15497	10000	100	15618	15660	15737	15610	15559

1000 unrolls and 10 iterations

Result (median cycles for code): 1.5458

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	92	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	bb	l1d tlb miss nonspec (c1)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10024	15539	116	334	175	333	24469	15436	9522	25	10010	10	10000	10	10000	50	724403	1	49	12351	15371	15444	14080	3	14231	10010	20	10000	20	10000	15380	15409	1	1	10021	10	9	2539	10	10	10	22875	22832	32827	0	0	24551	22717	10000	640	2	16	2	2	15351	10000	10	15469	15502	15426	15501	15389
10024	15440	116	337	172	335	24566	15454	9646	25	10010	10	10000	10	10000	50	724020	1	49	12390	15501	15449	14034	3	14211	10010	20	10000	20	10000	15490	15499	1	1	10021	10	9	2611	10	10	10	22849	22686	32766	0	0	24496	22735	10000	640	2	16	2	2	15380	10000	10	15476	15484	15508	15495	15408
10024	15362	115	335	167	334	24549	15479	9475	25	10010	10	10000	10	10000	50	726266	1	49	12335	15477	15434	13960	3	14160	10010	20	10000	20	10000	15366	15455	1	1	10021	10	9	2561	10	10	10	22756	22759	32760	0	0	24522	22778	10000	640	2	16	2	2	15369	10000	10	15491	15533	15580	15475	15401
10024	15474	115	334	179	344	24582	15459	9437	25	10010	10	10000	10	10000	50	725154	0	49	12410	15404	15447	14087	3	14194	10010	20	10000	20	10000	15376	15451	1	1	10021	10	9	2546	10	10	10	22742	22728	32803	0	0	24580	22822	10000	640	2	16	2	2	15358	10000	10	15473	15458	15482	15499	15382
10024	15514	117	341	177	342	24499	15429	9507	25	10010	10	10000	10	10000	50	722725	1	49	12394	15431	15448	14035	3	14228	10010	20	10000	20	10000	15440	15467	1	1	10021	10	9	2638	10	10	10	22798	22771	32699	0	0	24605	22798	10000	640	2	16	2	2	15431	10000	10	15467	15496	15475	15406	15454
10024	15474	115	329	172	339	24530	15443	9504	25	10010	10	10000	10	10000	50	722549	0	49	12400	15392	15440	14057	3	14143	10010	20	10000	20	10000	15462	15525	1	1	10021	10	9	2584	10	10	10	22771	22768	32790	0	0	24515	22694	10000	640	2	16	2	2	15355	10000	10	15442	15462	15491	15472	15471
10024	15475	116	332	173	333	24495	15454	9466	25	10010	10	10000	10	10000	50	726360	0	49	12366	15435	15547	14021	3	14087	10010	20	10000	20	10000	15471	15397	1	1	10021	10	9	2616	10	10	10	22675	22839	32667	0	0	24603	22703	10000	640	2	16	2	2	15296	10000	10	15425	15444	15543	15499	15421
10024	15375	116	337	179	340	24572	15373	9486	25	10010	10	10000	10	10000	50	725267	0	49	12445	15400	15469	14011	3	14177	10010	20	10000	20	10000	15447	15517	1	1	10021	10	9	2572	10	10	10	22816	22759	32840	1	0	25765	22701	10000	640	2	16	2	2	15360	10000	10	15411	15415	15441	15326	15431
10024	15449	117	335	177	335	24541	15374	9503	25	10010	10	10000	10	10000	50	725347	0	49	12386	15413	15474	14020	3	14149	10010	20	10000	20	10000	15457	15461	1	1	10021	10	9	2618	10	10	10	22767	22688	32710	1	0	24645	22790	10000	640	2	16	2	2	15262	10000	10	15526	15476	15381	15421	15424
10024	15411	116	341	167	335	24510	15395	9527	25	10010	10	10000	10	10000	50	723422	0	49	12402	15463	15521	13902	3	14164	10010	20	10000	20	10000	15398	15520	1	1	10021	10	9	2551	10	10	10	22768	22784	32767	0	0	24636	22771	10000	640	2	16	2	2	15326	10000	10	15488	15435	15447	15369	15477

PRFM (register, PLIL3STRM)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations