Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SUB (uxtw, 64-bit)

Test 1: uops

Code:

  sub x0, x0, w1, uxtw
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
100420351506110001735252000200010003257002035203515753184210001000200020354211100110000000731671117812000100020362036203620362036
100420351508410001735252000200010003257002035203515753184210001000200020354211100110000060731671117812000100020362036203620362036
100420351706110001735252000200010003257002035203515753184210001000200020354211100110000000731671117812000100020362036203620362036
100420351606110001735252000200010003257002035203515753184210001000200020354211100110000000731671117812000100020362036203620362036
100420351506110001735252000200010003257002035203515753184210001000200020354211100110000000731671117812000100020362036203620362036
100420351506110001735252000200010003257002035203515753184210001000200020354211100110000000731671117812000100020362036203620362036
100420351606110001735252000200010003257002035203515753184210001000200020354211100110000000731671117812000100020362036203620362036
100420351506110001735252000200010003257002035203515753184210001000200020354211100110000000731671117812000100020362036203620362036
100420351506110001735252000200010003257002035203515753184210001000200020354211100110000000731671117812000100020362036203620362036
100420351606110001735252000200010003257002035203515753184210001000200020354211100110000000731671117812000100020362036203620362036

Test 2: Latency 1->2

Code:

  sub x0, x0, w1, uxtw
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102042003515000305761100001980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001002000710159111979120000101002003620081200822021920036
1020420035150000033103100001980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001000100710159111979120000101002003620036200362003620036
10204200351500000061100001980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001000000710159111979120000101002003620036200362003620036
1020420035150010045661100001980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001000000710159111979120000101002003620036200362003620036
10204200351500000061100001980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001000000710159111979120000101002003620036200362003620036
10204200351500000061100001980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001000000710159111979120000101002003620036200362003620036
10204200351500000061100001980325201002010010100185342149169552008020035184293187001010010200202002003542111020110099100101001000000710159111979120000101002003620036200362003620036
10204200351500000061100001980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001000000710159111979120000101002022020036200362003620036
10204200351500000061100271980325201002010010100185342149169552003520035184293187001010010200202002003542111020110099100101001000000710159111979120000101002022020036200362003620036
1020420035150000061696100001980325201002010010100185342049169552003520035184293187001010010200202002003542411020110099100101001000000710159111979120000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)0318191e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1002420035150009103100001974325200102001010010185310491695520035200351845131871810010100202002020035421110021109101001010000640263221979220000100102003620036200362003620036
100242003515000061100001974325200102001010010185310491695520035200351845131871810010100202002020035421110021109101001010100640263221979220000100102003620036200362003620036
100242003515000061100001974325200102001010010185310491695520035200351845131871810010100202002020035421110021109101001010000640263221979220000100102003620036200362003620036
100242003515000061100001974325200102001010010185310491695520035200351845131871810010100202002020035421110021109101001010000640263221979220000100102003620036200362003620036
1002420035150000124100001974325200102001010010185310491695520035200351845131871810010100202002020035421110021109101001010000671263221979220000100102003620036200362003620036
100242003515000061100001974325200102001010010185310491695520035200351845131871810010100202002020035421110021109101001010000640263221979220000100102003620036200362003620036
100242003515000061100001974325200102001010010185310491695520035200351845131871810010100202002020035421110021109101001010100640263221979220000100102003620036200362003620036
100242003515000061100001974325200102001010010185310491695520035200351845131871810010100202002020035421110021109101001010000640263221979220000100102003620036200362003620036
1002420035150100611000019743252001020010100101853104916955200352003518451131871810010100202002020035421110021109101001010100640263221979220000100102003620036200362003620036
1002420035150000408100001974325200102001010010185310491695520035200351845131871810010100202002020035421110021109101001010100640263221979220000100102003620036200362003620036

Test 3: Latency 1->3

Code:

  sub x0, x1, w0, uxtw
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
102042003515066110000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100710159111979120000101002003620036200362003620036
102042003515006110000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100710159111979120000101002003620036200362003620036
102042003515006110000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100710159111979120000101002003620036200362003620036
1020420035150276110000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100710159111979120000101002003620036200362003620036
1020420035150366110000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100710159111979120000101002003620036200362003620036
1020420035150186110000197504620100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100710159111979120000101002003620036200362003620036
1020420035151186110000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100710159111979120000101002003620036200362003620036
102042003515006110000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100710159111979120000101002003620036200362003620036
102042003514906110000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100710159111979120000101002003620036200362003620036
1020420035150156110000198032520100201001010018534214916955200352003518429318700101001020020200200354211102011009910010100100710159111979120000101002003620036200362003620036

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)191e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
1002420035150000126100001974325200102001010010185310049169550200352003518451318718100101002020020200354211100211091010010100000640263221979220000100102003620036200362003620036
1002420035150000105100001974325200102001010010185310149169550200352003518451318718100101002020020200354211100211091010010100000640263221979220000100102003620036200362003620036
1002420035150000480100001974325200102001010010185310149169550200352003518451318718100101002020020200354211100211091010010100000640263221979220000100102003620036200362003620036
100242003515000061100001974325200102001010010185310149169550200352003518451318718100101002020020200354211100211091010010101030640263221979220000100102003620036200362003620036
100242003515000084100001974325200102001010010185310149169550200352003518451318718100101002020020200354211100211091010010101000640263221979220000100102003620036200362003620036
100242003515000061100001974325200102001010010185310149169550200352003518451318718100101002020020200354211100211091010010101000640263221979220000100102003620036200362003620036
100242003515000061100001974325200102001010010185310149169550200352003518451318718100101002020020200354211100211091010010100000640263221979220000100102003620036200362003620036
100242003515000082100001974325200102001010010185310149169550200352003518451318718100101002020020200354211100211091010010100000640263221979220000100102003620036200362003620036
1002420035150000103100001974325200102001010010185310049169550200352003518451318718100101002020020200354211100211091010010100000640363221979220000100102003620036200362003620036
1002420035150001884100001974325200102001010010185310049169550200352003518451318718100101002020020200354211100211091010010100000640263221979220000100102003620036200362003620036

Test 4: throughput

Count: 8

Code:

  sub x0, x8, w9, uxtw
  sub x1, x8, w9, uxtw
  sub x2, x8, w9, uxtw
  sub x3, x8, w9, uxtw
  sub x4, x8, w9, uxtw
  sub x5, x8, w9, uxtw
  sub x6, x8, w9, uxtw
  sub x7, x8, w9, uxtw
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3341

retire uop (01)cycle (02)03191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
802042676820100061800002609425160100160100801001643181492364526725267251661531667780100802001602002672539118020110099100801001000000051342221126717160000801002672626726267262672626726
8020426725200060336800002609425160100160100801001643181492364526725267311661531667780100802001602002672539118020110099100801001000000051105235526717160000801002672626726267262672626726
802042672520000061800002609425160100160100801001643181492364526725267311661531667780100802001602002672539118020110099100801001000000051102236226723160000801002672626726267262672626726
8020426731200024061800812437825160100160100803351643181492365126725267851661531667780332802001602002678940318020110099100801001000000051101221126717160000801002672626726267262673226726
80204267252001480324800002585225160100160300801001643181492364526725267251661531667780100802001602002672539118020110099100801001000000051101221126717160000801002672626726267262672626726
8020426725200012061800002609425160100160100801001643181492364526725267251661531667780100802001602002672539118020110099100801001000000051101225126717160000801002672626726267262672626726
802042672520000061800002609425160100160100801001643181492364526725267251661531667780100802001602002672539118020110099100801001000000051101221126717160000801002672626726267262672626726
8020426725200008861800002609425160100160302803101643181492364526725267251661531667780100802001602002684139118020110099100801001002230149851101221126717160025801002672626726267262672626726
8020426725200012061800002395625160100160100801001643181492364526725267251661531667780100802001602002672540118020110099100801001000000051101225526723160000801002672626726267262672626726
8020426725200012061800002609425160100160100801001643181492364526725267251661531668280125802001602002672539118020110099100801001000000051101221126717160000801002672626726267262672626726

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3339

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)5f6067696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
8002426807200016880000212802516001016001080010163142000492363126711267111662331668580010800201600202671139118002110910800101005020922132226704160000800102671226712267122671226712
8002426711200061800002128025160010160010800101631420104923631267112671116623316685800108002016002026711391180021109108001010050201322141126704160000800102671226712267122671226712
8002426711200061800002128025160010160010800101631420004923631267112671116623316685800108002016002026711391180021109108001010050201322161326704160000800102671226712267122671226712
8002426711200061800002128025160010160010800101631420104923631267112671116623316685800108002016002026711391180021109108001010050201222142226704160000800102671226712267122671226712
8002426711200061800002128025160010160010800101631420104923631267112671116623316685800108002016002026711391180021109108001010050201222141826704160000800102671226712267122671226712
8002426768200061800002128025160010160010800101631420104923631267112671116623316685800108002016002026711391180021109108001010050201122112026704160000800102671226712267122671226712
8002426711200061800002128025160010160010800101631420104923631267112671116623316685800108002016002026711391180021109108001010050201522141926704160000800102671226712267122671226712
8002426711200061800002128025160010160010800101631421104923631267112671116623316685800108002016002026711391180021109108001010050201622161326704160000800102671226712267122671226712
8002426711200084800002128025160010160010800101631420004923631267112671116623316685800108002016002026791391180021109108001010250201222161626704160000800102671226712267122671226712
8002426711200061800002128025160010160010800101631420104923631267112671116623316685800108002016002026711391180021109108001010050201622161326704160000800102671226712267122671226712