Firestorm: SMULL measurements

Code:

  smull x0, w0, w1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	3033	23	0	0	307	2809	25	1000	1000	1000	161686	1	40	3033	3033	2676	3	2891	1000	1000	2000	3033	296	1	1	1001	1000	0	0	73	2	16	2	2	2863	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	0	0	61	2809	25	1000	1000	1000	161686	0	40	3033	3033	2676	3	2891	1000	1000	2000	3033	296	1	1	1001	1000	0	0	73	2	16	2	2	2863	1000	1000	3034	3034	3034	3034	3034
1004	3033	24	0	0	61	2809	25	1000	1000	1000	161686	0	40	3033	3033	2676	16	2891	1000	1000	2000	3033	296	1	1	1001	1000	1	0	73	2	16	2	2	2863	1000	1000	3034	3034	3034	3034	3034
1004	3033	24	0	0	61	2809	25	1000	1000	1000	161686	1	40	3033	3033	2676	3	2891	1000	1000	2000	3033	296	1	1	1001	1000	0	0	73	2	16	2	2	2863	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	0	0	61	2809	25	1000	1000	1000	161686	0	40	3033	3033	2676	3	2891	1000	1000	2000	3033	296	1	1	1001	1000	0	0	73	2	16	2	2	2863	1000	1000	3034	3034	3034	3034	3034
1004	3033	22	0	0	912	2809	25	1000	1000	1000	161686	1	40	3033	3033	2676	3	2891	1061	1000	2000	3033	296	1	1	1001	1000	0	3	73	2	16	1	2	2863	1000	1000	3034	3034	3034	3034	3034
1004	3033	22	0	0	61	2809	25	1000	1000	1000	161686	1	40	3033	3033	2676	3	2891	1000	1000	2000	3033	296	1	1	1001	1000	0	0	73	2	16	2	2	2863	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	0	0	61	2809	25	1000	1000	1000	161686	1	40	3033	3033	2676	3	2891	1000	1000	2000	3033	296	1	1	1001	1000	0	0	73	2	16	2	2	2863	1000	1000	3034	3034	3034	3034	3034
1004	3033	23	0	0	61	2809	25	1000	1000	1000	161686	1	40	3033	3033	2676	3	2891	1000	1000	2000	3033	296	1	1	1001	1000	0	3	73	2	16	2	2	2863	1000	1000	3034	3034	3034	3034	3034
1004	3033	22	0	0	61	2809	25	1000	1000	1000	161686	0	40	3033	3033	2676	3	2891	1000	1000	2000	3033	296	1	1	1001	1000	0	0	73	2	16	2	2	2863	1000	1000	3034	3034	3034	3034	3034

Test 2: Latency 1->2

Code:

  smull x0, w0, w1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30033	225	24	61	29809	25	10100	10100	10100	1665186	1	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30070	290	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	255	61	29809	25	10100	10100	10100	1665186	0	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	2	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	51	61	29809	25	10100	10100	10100	1665186	0	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	45	61	29809	25	10100	10100	10100	1665186	0	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	36	61	29809	25	10100	10100	10100	1665186	0	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	224	96	61	29809	25	10100	10100	10100	1665186	0	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	12	61	29809	25	10100	10100	10100	1665186	0	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	224	3	61	29809	25	10100	10100	10100	1665186	0	49	26953	30033	30033	28561	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	61	29809	25	10100	10100	10100	1665186	0	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	224	0	61	29809	25	10100	10100	10100	1665186	0	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	710	1	16	1	1	29863	10000	10100	30034	30034	30034	30034	30034

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? int retires (ef)	f5	f6	f7	f8	fd
10024	30033	225	0	61	29809	25	10010	10010	10010	1664736	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	16	2	2	29864	10000	0	10010	30034	30034	30034	30034	30034
10024	30033	225	0	61	29809	25	10010	10010	10010	1664736	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	3	0	640	2	16	2	2	29864	10000	0	10010	30034	30034	30034	30034	30034
10024	30033	225	0	145	29809	25	10010	10010	10010	1664736	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	16	2	2	29864	10000	0	10010	30034	30034	30034	30034	30034
10024	30033	225	0	61	29809	25	10010	10010	10010	1664736	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	4	0	0	640	2	16	2	2	29864	10000	0	10010	30034	30034	30034	30034	30034
10024	30033	225	0	61	29809	25	10010	10010	10010	1664736	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	16	2	2	29864	10000	2	10010	30034	30034	30034	30034	30034
10024	30033	225	0	61	29809	25	10010	10010	10010	1664736	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	16	2	2	29864	10000	0	10010	30034	30034	30034	30034	30034
10024	30033	224	0	61	29809	25	10010	10010	10010	1664736	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	25	9	0	640	2	16	2	2	29864	10000	0	10010	30034	30034	30034	30034	30034
10024	30033	225	0	61	29809	25	10010	10010	10010	1664736	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	16	2	2	29864	10000	0	10010	30034	30034	30034	30034	30034
10024	30033	225	0	61	29809	25	10010	10010	10010	1664736	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	16	2	2	29864	10000	0	10010	30034	30034	30034	30034	30034
10024	30033	225	0	61	29809	25	10010	10010	10010	1664736	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	16	2	2	29864	10000	0	10010	30034	30034	30034	30034	30034

Test 3: Latency 1->3

Code:

  smull x0, w1, w0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30033	225	0	93	61	29809	25	10100	10100	10100	1665186	1	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	0	710	2	16	2	2	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	15	61	29809	25	10100	10100	10100	1665186	1	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	0	710	2	16	2	2	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	61	29809	25	10100	10100	10100	1665186	1	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	0	710	2	16	2	2	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	15	61	29809	25	10100	10100	10100	1665186	1	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	0	710	3	16	2	2	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	33	61	29809	25	10100	10100	10100	1665186	1	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	0	710	2	16	2	2	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	61	29809	25	10100	10100	10100	1665186	0	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	0	710	2	16	2	2	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	213	61	29809	25	10100	10100	10100	1665186	0	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	0	710	2	16	2	2	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	0	61	29809	25	10100	10100	10100	1665186	0	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	0	710	2	16	2	2	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	225	0	66	61	29809	25	10100	10100	10100	1665186	1	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	0	710	2	16	2	2	29863	10000	10100	30034	30034	30034	30034	30034
10204	30033	224	0	0	61	29809	25	10100	10100	10100	1665186	0	49	26953	30033	30033	28526	3	28741	10100	10200	20200	30033	290	1	1	10201	100	99	100	10100	100	0	0	0	0	710	2	16	2	2	29863	10000	10100	30034	30034	30034	30034	30034

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30033	225	61	29809	25	10010	10010	10010	1664736	1	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	61	29809	25	10010	10010	10010	1664736	1	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	61	29809	25	10010	10010	10010	1664736	0	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	61	29809	25	10010	10010	10010	1664736	0	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	61	29809	25	10010	10010	10010	1664736	0	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	61	29809	25	10010	10010	10010	1664736	1	98	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	11	0	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	61	29809	25	10010	10010	10010	1664736	0	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	61	29809	25	10010	10010	10010	1664736	1	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	1	0	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	61	29809	25	10010	10010	10010	1664736	1	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034
10024	30033	225	61	29809	25	10010	10010	10010	1664736	0	49	26953	30033	30033	28548	3	28763	10010	10020	20020	30033	296	1	1	10021	10	9	10	10010	10	0	0	0	0	0	640	2	16	2	2	29864	10000	10010	30034	30034	30034	30034	30034

Test 4: throughput

Count: 8

Code:

  smull x0, w8, w9
  smull x1, w8, w9
  smull x2, w8, w9
  smull x3, w8, w9
  smull x4, w8, w9
  smull x5, w8, w9
  smull x6, w8, w9
  smull x7, w8, w9

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	40052	313	0	0	0	0	0	0	0	40	25	80100	80100	80100	400500	49	36955	40035	40035	29970	3	29993	80100	80200	160200	40035	90	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	2	16	1	1	40032	80000	80100	40036	40036	40036	40036	40036
80204	40035	300	0	0	0	0	0	0	0	40	25	80100	80100	80100	400500	49	36955	40035	40035	29970	3	29993	80100	80200	160200	40035	90	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	16	1	1	40032	80000	80100	40036	40036	40036	40126	40082
80204	40035	300	0	0	0	0	0	0	0	208	25	80100	80100	80100	400500	49	36955	40035	40035	29970	3	29993	80100	80200	160200	40035	90	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	16	1	1	40032	80000	80100	40036	40036	40036	40036	40036
80204	40035	300	0	0	0	0	0	0	0	40	25	80100	80100	80100	400500	49	36955	40035	40035	29970	3	29993	80100	80200	160200	40035	90	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	16	1	1	40032	80000	80100	40036	40036	40036	40036	40036
80204	40035	300	0	0	0	0	0	0	0	40	25	80100	80100	80100	400500	49	36955	40035	40035	29970	3	29993	80100	80200	160200	40035	90	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	16	1	1	40032	80000	80100	40036	40036	40036	40036	40036
80204	40035	300	0	0	0	0	0	0	0	40	25	80100	80100	80100	400500	49	36955	40035	40035	29970	3	29993	80100	80200	160200	40035	90	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	16	1	1	40032	80000	80100	40036	40036	40036	40036	40036
80204	40035	300	0	0	0	0	0	0	0	40	25	80100	80100	80100	400500	49	36955	40035	40035	29970	3	29993	80100	80200	160200	40035	90	1	1	80201	100	99	100	80100	100	0	0	0	0	3	5110	1	16	1	1	40032	80000	80100	40036	40036	40036	40218	40036
80204	40035	300	0	0	0	0	0	0	0	40	25	80100	80100	80100	400500	49	36955	40035	40035	29970	3	29993	80100	80200	160200	40035	90	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	16	1	1	40032	80000	80100	40036	40036	40036	40036	40036
80204	40035	300	0	0	0	0	0	0	0	40	25	80100	80100	80100	400500	49	36955	40035	40035	29970	3	29993	80100	80200	160200	40035	90	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	16	1	1	40032	80000	80100	40036	40036	40036	40036	40036
80204	40035	300	0	0	0	0	0	0	0	40	25	80100	80100	80100	400500	49	36955	40035	40035	29970	3	29993	80100	80200	160200	40035	90	1	1	80201	100	99	100	80100	100	0	0	0	0	0	5110	1	16	1	1	40032	80000	80100	40036	40036	40036	40036	40036

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? int retires (ef)	f5	f6	f7	f8	fd
80024	40049	300	0	0	0	0	0	0	0	61	25	80010	80010	80010	400050	1	49	36955	40035	40035	29992	3	30015	80010	80020	160020	40035	90	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	0	8	16	0	8	6	40032	80000	4	80010	40036	40036	40036	40036	40036
80024	40035	299	0	0	0	0	0	0	0	40	25	80010	80010	80010	400050	1	49	36955	40035	40035	29992	3	30015	80010	80020	160020	40035	90	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	0	8	16	0	8	8	40032	80000	0	80010	40036	40036	40036	40036	40036
80024	40035	300	0	0	0	0	0	0	0	40	25	80010	80010	80010	400050	1	49	36955	40035	40035	29992	3	30015	80010	80020	160020	40035	90	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	0	8	16	0	7	13	40032	80000	0	80010	40036	40036	40036	40036	40036
80024	40035	300	0	0	0	0	0	0	0	40	25	80010	80010	80010	400050	1	49	36955	40035	40035	29992	3	30015	80010	80020	160020	40035	90	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	0	7	16	0	6	11	40032	80000	0	80010	40036	40036	40036	40036	40036
80024	40035	300	0	0	0	0	0	0	0	40	25	80010	80010	80010	400230	1	49	36955	40035	40035	29992	3	30015	80052	80020	160020	40035	90	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	0	7	16	0	9	6	40032	80000	0	80010	40036	40036	40036	40036	40036
80024	40035	300	0	0	0	0	0	0	0	40	25	80010	80010	80010	400050	0	49	36955	40035	40035	29992	3	30015	80010	80020	160020	40035	90	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	0	10	16	0	5	7	40032	80000	0	80010	40036	40036	40036	40036	40036
80024	40035	299	0	0	0	0	0	0	0	40	25	80010	80010	80010	400050	1	49	36955	40035	40035	29992	3	30015	80010	80020	160020	40035	90	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	0	10	16	0	10	9	40032	80000	0	80010	40036	40036	40036	40036	40036
80024	40035	299	0	0	0	0	0	0	0	40	25	80010	80010	80052	400050	1	49	36955	40035	40035	29992	3	30015	80010	80020	160020	40035	90	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	0	10	16	0	9	6	40032	80000	0	80010	40036	40036	40036	40036	40036
80024	40035	300	0	0	0	0	0	0	0	40	25	80010	80010	80010	400050	1	49	36955	40035	40035	29992	3	30015	80010	80020	160020	40035	90	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	0	6	16	0	8	7	40032	80000	0	80010	40036	40036	40036	40036	40036
80024	40035	299	0	0	0	0	0	0	0	40	25	80010	80010	80010	400050	1	49	36955	40035	40035	29992	3	30015	80010	80020	160020	40035	90	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	5020	0	5	16	0	9	8	40032	80000	0	80010	40036	40036	40036	40036	40036

SMULL

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations