Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

MSR (DIT)

Test 1: uops

Code:

  msr s3_3_c4_c2_5, x0

Initialization

  mrs x0, s3_3_c4_c2_5

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	? int output thing (e9)
1004	10024	1001	1001	1001
1004	10024	1001	1001	1001
1004	10024	1001	1001	1001
1004	10024	1001	1001	1001
1004	10024	1001	1001	1001
1004	10024	1001	1001	1001
1004	10024	1001	1001	1001
1004	10024	1001	1001	1001
1004	10024	1001	1001	1001
1004	10024	1001	1001	1001

Test 2: throughput

Code:

  msr s3_3_c4_c2_5, x0

Initialization

  mrs x0, s3_3_c4_c2_5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0024

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	100024	10101	10101	100	0	300	0	100	200	0	200	10001	100
10204	100024	10101	10101	100	0	300	0	100	200	0	200	10001	100
10204	100024	10101	10101	100	0	300	0	100	200	0	200	10001	100
10204	100024	10101	10101	100	0	300	0	100	200	0	200	10001	100
10204	100024	10101	10101	100	0	300	0	100	200	0	200	10001	100
10204	100024	10101	10101	100	0	300	0	100	200	0	200	10001	100
10204	100024	10101	10101	100	0	300	0	100	200	0	200	10001	100
10204	100024	10101	10101	100	0	300	0	100	200	0	200	10001	100
10204	100024	10101	10101	100	289	7474	2430	795	754	329	200	10001	100
10204	100024	10101	10101	100	0	300	0	100	200	0	200	10001	100

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0024

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	100024	10011	10011	10	30	10	20	20	10001	10
10024	100024	10011	10011	10	30	10	20	20	10001	10
10024	100024	10011	10011	10	30	10	20	20	10001	10
10024	100024	10011	10011	10	30	10	20	20	10001	10
10024	100024	10011	10011	10	30	10	20	20	10001	10
10025	100048	10011	10011	10	30	10	20	20	10001	10
10024	100024	10011	10011	10	30	10	20	20	10001	10
10024	100024	10011	10011	10	30	10	20	20	10001	10
10024	100024	10011	10011	10	30	10	20	20	10001	10
10024	100024	10011	10011	10	30	10	20	20	10001	10