Icestorm: CRC32B measurements

Code:

  crc32b w0, w0, w1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000

Test 2: Latency 1->2

Code:

  crc32b w0, w0, w1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	30030	10101	10101	10100	260150	10100	10206	20212	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	30030	10021	10021	10020	259907	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010
10025	30060	10026	10026	10034	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010

Test 3: Latency 1->3

Code:

  crc32b w0, w1, w0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10204	30030	10101	10101	10100	260144	10100	10206	20212	0	10001	0	0	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	0	10001	0	0	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	0	10001	0	0	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	0	10001	0	0	10100
10204	30030	10101	10101	10100	260156	10100	10208	20256	0	10006	0	0	10100
10204	30030	10101	10101	10100	260156	10100	10208	21856	1206	10690	596	3	11030
10204	30030	10101	10101	10100	260156	10100	10208	20216	0	10001	0	0	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	0	10001	0	0	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	0	10001	0	0	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	0	10001	0	0	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	30030	10021	10021	10020	259907	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010

Test 4: throughput

Count: 8

Code:

  crc32b w0, w8, w9
  crc32b w1, w8, w9
  crc32b w2, w8, w9
  crc32b w3, w8, w9
  crc32b w4, w8, w9
  crc32b w5, w8, w9
  crc32b w6, w8, w9
  crc32b w7, w8, w9

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	80044	80104	80104	80105	0	240315	0	0	80105	80210	0	0	160224	80004	80100
80204	80044	80104	80104	80105	0	240315	0	0	80105	80212	0	0	160224	80004	80100
80204	80034	80104	80104	80105	0	240315	0	0	80105	80212	0	0	160224	80004	80100
80204	80034	80104	80104	80105	0	240315	0	0	80105	80212	0	0	160224	80004	80100
80204	80034	80104	80104	80105	0	240315	0	0	80105	80212	0	0	160224	80004	80100
80205	80066	80120	80120	80124	0	240315	0	0	80105	80212	0	0	160224	80004	80100
80204	80034	80104	80104	80105	0	240315	0	0	80105	80212	0	0	160224	80004	80100
80204	80034	80104	80104	80105	0	240315	0	0	80105	80212	0	0	160224	80004	80100
80204	80034	80104	80104	80105	0	240315	0	0	80105	80212	0	0	160224	80004	80100
80204	80034	80104	80104	80105	0	240315	0	0	80105	80212	0	0	160224	80004	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	80035	80025	80025	80026	0	240132	0	80045	80058	0	160044	80015	80010
80024	80035	80025	80025	80026	0	240060	0	80020	80020	0	160020	80011	80010
80024	80032	80021	80021	80020	0	240132	0	80045	80058	0	160020	80011	80010
80024	80032	80021	80021	80020	0	240060	0	80020	80020	0	160020	80011	80010
80024	80032	80021	80021	80020	0	240060	0	80020	80020	0	160020	80011	80010
80024	80032	80021	80021	80020	0	240060	0	80020	80020	0	160020	80011	80010
80024	80032	80021	80021	80020	0	240060	0	80020	80020	0	160020	80011	80010
80024	80032	80021	80021	80020	0	240060	0	80020	80020	0	160020	80011	80010
80024	80032	80021	80021	80020	0	240060	0	80020	80020	0	160020	80011	80010
80025	80067	80041	80041	80045	0	240060	0	80020	80020	0	160020	80011	80010

CRC32B

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations