Icestorm: LDR (pre-index, 64-bit) measurements

Code:

  ldr x0, [x6, #8]!

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
2005	1224	2032	1019	1013	1036	1000	20868	17558	2000	1000	1000	1000	1000	1001	1000	1000
2004	1101	2001	1001	1000	1000	1000	20738	17615	2000	1000	1000	1000	1000	1001	1000	1000
2004	1088	2001	1001	1000	1000	1000	21230	17806	2000	1000	1000	1000	1000	1001	1000	1000
2004	1112	2001	1001	1000	1000	1000	21282	17804	2000	1000	1000	1000	1000	1001	1000	1000
2004	1085	2001	1001	1000	1000	1000	21343	18707	2000	1000	1000	1000	1000	1001	1000	1000
2004	1087	2001	1001	1000	1000	1000	21276	17806	2000	1000	1000	1000	1000	1001	1000	1000
2004	1113	2001	1001	1000	1000	1000	21310	18003	2000	1000	1000	1000	1000	1001	1000	1000
2004	1085	2001	1001	1000	1000	1000	21236	17803	2000	1000	1000	1000	1000	1001	1000	1000
2004	1087	2001	1001	1000	1000	1000	21238	17771	2000	1000	1000	1000	1000	1001	1000	1000
2004	1088	2001	1001	1000	1000	1000	21264	17802	2000	1000	1000	1000	1000	1001	1000	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldr x0, [x6, #8]!
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0110

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50209	71425	50161	40156	10005	40247	10003	1851635	535079	50109	40212	10004	70221	10004	40003	10000	40100
50204	70114	50103	40103	10000	40106	10003	1850415	534815	50109	40212	10004	70221	10004	40003	10000	40100
50204	70110	50103	40103	10000	40106	10003	1850469	534833	50109	40212	10004	70221	10004	40003	10000	40100
50204	70110	50103	40103	10000	40106	10003	1850469	534833	50109	40212	10004	70221	10004	40003	10000	40100
50204	70110	50103	40103	10000	40106	10003	1850415	534815	50109	40212	10004	70221	10004	40003	10000	40100
50204	70110	50103	40103	10000	40106	10003	1850469	534833	50109	40212	10004	70221	10004	40003	10000	40100
50204	70110	50103	40103	10000	40106	10003	1850469	534833	50109	40212	10004	70221	10004	40003	10000	40100
50204	70110	50103	40103	10000	40106	10003	1850469	534833	50109	40212	10004	70221	10004	40003	10000	40100
50204	70110	50103	40103	10000	40106	10003	1850469	534833	50109	40212	10004	70221	10004	40003	10000	40100
50204	70110	50103	40103	10000	40106	10003	1850469	534833	50109	40212	10004	70221	10004	40003	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0167

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50029	71373	50070	40065	10005	40156	10003	1850186	534975	0	50019	40032	10004	0	70020	10000	40004	10000	40010
50024	70101	50014	40014	10000	40010	10000	1850174	535029	0	50010	40020	10000	0	70020	10000	40004	10000	40010
50024	70090	50013	40013	10000	40010	10000	1850309	535074	0	50010	40020	10000	0	70020	10000	40004	10000	40010
50024	70141	50013	40013	10000	40010	10000	1851092	535332	0	50010	40020	10000	0	70020	10000	40004	10000	40010
50024	70090	50013	40013	10000	40010	10000	1850174	535029	0	50010	40020	10000	0	70020	10000	40004	10000	40010
50024	70090	50013	40013	10000	40010	10000	1850174	535029	0	50010	40020	10000	0	70109	10013	40015	10000	40010
50024	70113	50014	40014	10000	40010	10000	1850741	535218	0	50010	40020	10000	0	70020	10000	40004	10000	40010
50024	70139	50013	40013	10000	40010	10000	1850849	535250	0	50010	40020	10000	0	70020	10000	40004	10000	40010
50024	70156	50013	40013	10000	40010	10000	1850876	535262	0	50010	40020	10000	0	70020	10000	40004	10000	40010
50025	70175	50026	40024	10002	40050	10000	1850174	535029	0	50010	40020	10000	0	70020	10000	40004	10000	40010

Test 3: throughput

Count: 8

Code:

  ldr x0, [x6, #8]!
  ldr x0, [x7, #8]!
  ldr x0, [x8, #8]!
  ldr x0, [x9, #8]!
  ldr x0, [x10, #8]!
  ldr x0, [x11, #8]!
  ldr x0, [x12, #8]!
  ldr x0, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5407

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160209	44205	160412	80312	80100	80315	80012	240810	642823	160124	80212	80012	80212	80012	80009	80000	80100
160204	43252	160107	80107	80000	80110	80011	240815	645354	160123	80212	80012	80212	80012	80009	80000	80100
160205	43335	160181	80150	80031	80153	80011	240838	642754	160123	80212	80012	80212	80012	80009	80000	80100
160204	43250	160109	80109	80000	80112	80009	240845	642031	160119	80210	80010	80212	80012	80009	80000	80100
160204	43246	160107	80107	80000	80110	80009	240815	641165	160121	80212	80012	80210	80010	80007	80000	80100
160204	43248	160109	80109	80000	80112	80011	240814	639221	160123	80212	80012	80212	80012	80009	80000	80100
160204	43247	160109	80109	80000	80112	80011	240842	640650	160123	80212	80012	80212	80012	80009	80000	80100
160204	43246	160109	80109	80000	80112	80012	240800	636113	160124	80212	80012	80212	80012	80009	80000	80100
160204	43246	160109	80109	80000	80112	80012	240815	642812	160124	80212	80012	80212	80012	80009	80000	80100
160204	43249	160110	80109	80001	80112	80011	240801	645580	160123	80212	80012	80212	80012	80009	80000	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5404

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160029	44414	160327	80223	80104	80226	80008	240340	643711	160030	80032	80012	80020	80000	80001	80000	80010
160024	43228	160011	80011	80000	80010	80000	240304	644195	160010	80020	80000	80020	80000	80001	80000	80010
160024	43229	160011	80011	80000	80010	80000	240304	644485	160010	80020	80000	80020	80000	80001	80000	80010
160024	43229	160011	80011	80000	80010	80000	240304	645730	160010	80020	80000	80020	80000	80001	80000	80010
160024	43229	160011	80011	80000	80010	80000	240304	641466	160010	80020	80000	80020	80000	80001	80000	80010
160024	43232	160011	80011	80000	80010	80164	240810	645508	160338	80184	80164	80020	80000	80001	80000	80010
160024	43229	160011	80011	80000	80010	80000	240304	643143	160010	80020	80000	80020	80000	80001	80000	80010
160024	43229	160011	80011	80000	80010	80000	240304	642720	160010	80020	80000	80020	80000	80001	80000	80010
160024	43229	160011	80011	80000	80010	80000	240304	643693	160010	80020	80000	80020	80000	80001	80000	80010
160024	43229	160011	80011	80000	80010	80000	240304	645595	160010	80020	80000	80020	80000	80001	80000	80010

LDR (pre-index, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations