Icestorm: LDRSB (unsigned offset, 64-bit) measurements

Code:

  ldrsb x0, [x6, #8]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	702	1027	1	1026	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	552	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb x0, [x6, #8]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70152	40108	30107	10001	30130	10003	1859485	693973	40106	30212	10004	60224	10004	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	10004	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	10004	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	10004	30003	10000	30100
40205	70133	40111	30109	10002	30135	10015	1859953	694151	40150	30247	10017	60224	10004	30003	10000	30100
40204	70055	40103	30103	10000	30103	10003	1859662	694096	40106	30212	10004	60224	10004	30003	10000	30100
40204	70047	40103	30103	10000	30103	10015	1861834	694956	40150	30251	10017	60224	10004	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	10004	30003	10000	30100
40204	70047	40103	30103	10000	30103	10003	1859581	694063	40106	30212	10004	60224	10004	30003	10000	30100
40204	70047	40103	30103	10000	30103	10015	1861708	694862	40150	30247	10017	60224	10004	30003	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70158	40018	30017	10001	30040	10000	1859658	694689	40010	30020	10000	60020	10000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1861353	695402	40010	30020	10000	60020	10000	30003	10000	30010
40024	70060	40013	30013	10000	30010	10000	1859787	694767	40010	30020	10000	60020	10000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	30010

Test 3: throughput

Count: 8

Code:

  ldrsb x0, [x6, #8]
  ldrsb x0, [x6, #8]
  ldrsb x0, [x6, #8]
  ldrsb x0, [x6, #8]
  ldrsb x0, [x6, #8]
  ldrsb x0, [x6, #8]
  ldrsb x0, [x6, #8]
  ldrsb x0, [x6, #8]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40172	80127	101	80026	100	80008	300	244262	80108	200	80012	200	80012	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	80012	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	80012	1	80000	100
80205	40102	80138	101	80037	100	80008	300	640142	80108	200	80012	200	80012	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	80012	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	80012	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	80012	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	80012	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	80012	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40282	80035	11	80024	10	80008	30	400190	80018	20	80012	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640040	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	80000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640094	80010	20	80000	20	80000	1	80000	10
80025	40102	80044	11	80033	10	80000	30	640094	80010	20	80000	20	80000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640040	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	80000	1	80000	10

LDRSB (unsigned offset, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations