Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
mrs x0, cntpct_el0
(no loop instructions)
Retires: 1.000
Issues: 1.000
Integer unit issues: 1.001
Load/store unit issues: 0.000
SIMD/FP unit issues: 0.000
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | ? int output thing (e9) | ? int retires (ef) |
1004 | 1279 | 1001 | 1001 | 1001 | 1000 |
1004 | 1279 | 1001 | 1001 | 1001 | 1000 |
1004 | 1279 | 1001 | 1001 | 1001 | 1000 |
1004 | 1279 | 1001 | 1001 | 1001 | 1000 |
1004 | 1279 | 1001 | 1001 | 1001 | 1000 |
1004 | 1279 | 1001 | 1001 | 1001 | 1000 |
1004 | 1279 | 1001 | 1001 | 1001 | 1000 |
1004 | 1279 | 1001 | 1001 | 1001 | 1000 |
1004 | 1279 | 1001 | 1001 | 1001 | 1000 |
1004 | 1279 | 1001 | 1001 | 1001 | 1000 |
Count: 8
Code:
mrs x0, cntpct_el0 mrs x1, cntpct_el0 mrs x2, cntpct_el0 mrs x3, cntpct_el0 mrs x4, cntpct_el0 mrs x5, cntpct_el0 mrs x6, cntpct_el0 mrs x7, cntpct_el0
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 1.2504
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
80204 | 100053 | 80101 | 80101 | 100 | 300 | 100 | 200 | 200 | 80001 | 80100 |
80205 | 100073 | 80109 | 80109 | 100 | 300 | 100 | 200 | 200 | 80001 | 80100 |
80204 | 100035 | 80101 | 80101 | 100 | 300 | 100 | 200 | 200 | 80001 | 80100 |
80204 | 100035 | 80101 | 80101 | 100 | 300 | 100 | 200 | 200 | 80001 | 80100 |
80204 | 100035 | 80101 | 80101 | 100 | 300 | 100 | 200 | 200 | 80001 | 80100 |
80204 | 100035 | 80101 | 80101 | 100 | 300 | 100 | 200 | 200 | 80001 | 80100 |
80204 | 100035 | 80101 | 80101 | 100 | 300 | 100 | 200 | 202 | 80009 | 80100 |
80204 | 100035 | 80101 | 80101 | 100 | 300 | 100 | 200 | 200 | 80001 | 80100 |
80204 | 100035 | 80101 | 80101 | 100 | 300 | 100 | 200 | 200 | 80001 | 80100 |
80204 | 100035 | 80101 | 80101 | 100 | 300 | 100 | 200 | 200 | 80001 | 80100 |
Result (median cycles for code divided by count): 1.2504
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
80024 | 100053 | 80011 | 80011 | 10 | 30 | 10 | 20 | 20 | 80001 | 80010 |
80024 | 100029 | 80011 | 80011 | 10 | 30 | 10 | 20 | 20 | 80009 | 80010 |
80024 | 100029 | 80011 | 80011 | 10 | 30 | 10 | 20 | 20 | 80001 | 80010 |
80024 | 100029 | 80011 | 80011 | 10 | 30 | 10 | 20 | 20 | 80001 | 80010 |
80024 | 100029 | 80011 | 80011 | 10 | 30 | 10 | 20 | 20 | 80001 | 80010 |
80024 | 100029 | 80011 | 80011 | 10 | 30 | 10 | 20 | 20 | 80001 | 80010 |
80024 | 100029 | 80011 | 80011 | 10 | 30 | 10 | 20 | 20 | 80001 | 80010 |
80024 | 100029 | 80011 | 80011 | 10 | 30 | 10 | 20 | 20 | 80001 | 80010 |
80024 | 100029 | 80011 | 80011 | 10 | 30 | 10 | 20 | 20 | 80001 | 80010 |
80024 | 100029 | 80011 | 80011 | 10 | 30 | 10 | 20 | 20 | 80001 | 80010 |