Icestorm: NEG (register, lsr, 64-bit) measurements

Code:

  neg x0, x0, lsr #17

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	1000	2001	1000

Test 2: Latency 1->2

Code:

  neg x0, x0, lsr #17

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	20030	20101	20101	0	0	10104	0	529143	10104	10210	10212	20001	10100
10204	20030	20101	20101	0	0	10104	0	529143	10104	10210	10212	20001	10100
10204	20030	20101	20101	0	0	10104	0	529186	10104	10212	10212	20001	10100
10204	20030	20101	20101	0	0	10104	0	529186	10104	10212	10212	20001	10100
10204	20030	20101	20101	0	0	10104	0	529186	10104	10212	10212	20001	10100
10204	20030	20101	20101	0	0	10104	0	529186	10104	10212	10212	20001	10100
10204	20030	20101	20101	0	0	10104	0	530160	10176	10294	10212	20001	10100
10204	20030	20101	20101	0	0	10104	0	530174	10176	10296	10212	20001	10100
10204	20030	20101	20101	0	0	10104	0	529186	10104	10212	10213	20001	10100
38529	72976	46917	37300	64	9553	27555	55	529186	10104	10212	10212	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10024	20030	20021	20021	10025	529220	10025	10034	10020	0	0	20011	0	0	10010
10025	20060	20035	20035	10058	529253	10020	10020	10020	0	0	20011	0	0	10010
10024	20030	20021	20021	10020	529253	10020	10020	10020	0	0	20011	0	0	10010
10024	20030	20021	20021	10020	529253	10020	10020	10020	0	0	20011	0	0	10010
10024	20030	20021	20021	10020	529253	10020	10020	10020	0	0	20011	0	0	10010
10024	20030	20021	20021	10020	529253	10020	10020	10020	0	0	20011	0	0	10010
10024	20030	20021	20021	10020	529253	10020	10020	10020	0	0	20011	0	0	10010
10024	20030	20021	20021	10020	529253	10020	10020	10020	0	0	20011	0	0	10010
10024	20030	20021	20021	10020	529253	10020	10020	10020	0	0	20011	0	0	10010
10024	20030	20021	20021	10020	529253	10020	10020	10020	0	0	20011	0	0	10010

Test 3: throughput

Count: 8

Code:

  neg x0, x8, lsr #17
  neg x1, x8, lsr #17
  neg x2, x8, lsr #17
  neg x3, x8, lsr #17
  neg x4, x8, lsr #17
  neg x5, x8, lsr #17
  neg x6, x8, lsr #17
  neg x7, x8, lsr #17

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80204	53429	160118	160118	80131	0	1360036	0	0	80130	80236	0	0	80236	0	0	160016	0	0	80100
80204	53404	160117	160117	80130	0	1360838	0	0	80130	80236	0	0	80236	0	0	160017	0	0	80100
80204	53404	160117	160117	80130	0	1360838	0	0	80130	80236	0	0	80236	0	0	160017	0	0	80100
80204	53404	160117	160117	80130	0	1360838	0	0	80130	80236	0	0	80236	0	0	160018	0	0	80100
80204	53427	160116	160116	80130	0	1360566	0	0	80130	80236	0	0	147832	24091	0	237464	13702	16	132337
80204	53427	160116	160116	80130	0	1360566	0	0	80130	80236	0	0	80236	0	0	160017	0	0	80100
80204	53404	160117	160117	80130	0	1360838	0	0	80130	80236	0	0	80236	0	0	160017	0	0	80100
80204	53404	160117	160117	80130	0	1360838	0	0	80130	80236	0	0	80236	0	0	160017	0	0	80100
80204	53404	160117	160117	80130	0	1360838	0	0	80130	80236	0	0	80236	0	0	160017	0	0	80100
80204	53404	160117	160117	80130	0	1360838	0	0	80130	80236	0	0	80236	0	0	160017	0	0	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6671

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80024	53402	160039	160039	80051	1359903	80020	80020	80020	0	0	160011	0	0	80010
80024	53371	160021	160021	80020	1359903	80020	80020	80020	0	0	160011	0	0	80010
80024	53371	160021	160021	80020	1359903	80020	80020	80020	0	0	160011	0	0	80010
80024	53371	160021	160021	80020	1359903	80020	80020	80020	0	0	160011	0	0	80010
80024	53371	160021	160021	80020	1359903	80020	80020	80020	0	0	160011	0	0	80010
80024	53371	160021	160021	80020	1359903	80020	80020	80020	0	0	160011	0	0	80010
80024	53371	160021	160021	80020	1359903	80020	80020	80020	0	0	160011	0	0	80010
80024	53371	160021	160021	80020	1359903	80020	80020	80020	0	0	160011	0	0	80010
80024	53371	160021	160021	80020	1359903	80020	80020	80020	0	0	160011	0	0	80010
80024	53371	160021	160021	80020	1359903	80020	80020	80020	0	0	160011	0	0	80010

NEG (register, lsr, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations