Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
casal w0, w1, [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0
(no loop instructions)
Retires (minus 70 nops): 4.000
Issues: 3.000
Integer unit issues: 0.001
Load/store unit issues: 3.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 74006 | 35767 | 3007 | 1 | 3006 | 3000 | 15033 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34414 | 3001 | 1 | 3000 | 3000 | 15033 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34345 | 3001 | 1 | 3000 | 3000 | 15020 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34348 | 3001 | 1 | 3000 | 3000 | 15033 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 35051 | 3001 | 1 | 3000 | 3000 | 15020 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34877 | 3001 | 1 | 3000 | 3000 | 15039 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34706 | 3001 | 1 | 3000 | 3000 | 15022 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34291 | 3001 | 1 | 3000 | 3000 | 15022 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34302 | 3001 | 1 | 3000 | 3000 | 15022 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34296 | 3001 | 1 | 3000 | 3000 | 15022 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
Code:
casal w0, w1, [x6] add x6, x6, 4
(fused SUBS/B.cc loop)
Result (median cycles for code): 9.0054
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) |
| 50210 | 90354 | 41853 | 11790 | 30063 | 11789 | 30003 | 42893 | 355179 | 0 | 44268 | 20201 | 30003 | 0 | 20201 | 60006 | 0 | 14167 | 30000 | 0 | 20100 |
| 50204 | 90058 | 44268 | 14267 | 30001 | 14265 | 30003 | 42862 | 355079 | 0 | 44268 | 20201 | 30003 | 0 | 20223 | 60072 | 0 | 12737 | 30000 | 0 | 20100 |
| 50204 | 90051 | 44268 | 14267 | 30001 | 14265 | 30003 | 42888 | 355211 | 0 | 44268 | 20201 | 30003 | 0 | 20201 | 60006 | 0 | 14167 | 30000 | 0 | 20100 |
| 50204 | 90051 | 44268 | 14267 | 30001 | 14265 | 30003 | 42862 | 355081 | 0 | 44268 | 20201 | 30003 | 0 | 20201 | 60006 | 0 | 14167 | 30000 | 0 | 20100 |
| 50204 | 90051 | 44268 | 14267 | 30001 | 14265 | 30003 | 42862 | 355082 | 0 | 44268 | 20201 | 30003 | 0 | 20201 | 60006 | 0 | 14167 | 30000 | 0 | 20100 |
| 50204 | 90058 | 44268 | 14267 | 30001 | 14265 | 30003 | 42855 | 355064 | 0 | 44268 | 20201 | 30003 | 0 | 20201 | 60006 | 0 | 14167 | 30000 | 0 | 20100 |
| 50204 | 90051 | 44268 | 14267 | 30001 | 14265 | 30003 | 42885 | 355337 | 0 | 44268 | 20201 | 30003 | 0 | 20201 | 60006 | 0 | 14167 | 30000 | 0 | 20100 |
| 50204 | 90084 | 44271 | 14270 | 30001 | 14265 | 30003 | 42886 | 355113 | 0 | 44268 | 20201 | 30003 | 0 | 20201 | 60006 | 0 | 14167 | 30000 | 0 | 20100 |
| 50204 | 90054 | 44268 | 14267 | 30001 | 14265 | 30003 | 42886 | 355140 | 0 | 44268 | 20201 | 30003 | 0 | 20201 | 60006 | 0 | 14167 | 30000 | 0 | 20100 |
| 50204 | 90054 | 44268 | 14267 | 30001 | 14265 | 30003 | 42886 | 355142 | 0 | 44268 | 20201 | 30003 | 0 | 20201 | 60006 | 0 | 14167 | 30000 | 0 | 20100 |
Result (median cycles for code): 9.0060
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) |
| 50030 | 90345 | 41760 | 11697 | 0 | 30063 | 11698 | 0 | 30003 | 42563 | 355313 | 44178 | 20021 | 30003 | 20043 | 60072 | 12057 | 30000 | 0 | 20010 |
| 50024 | 90058 | 44176 | 14176 | 0 | 30000 | 14175 | 0 | 30000 | 42563 | 355289 | 44175 | 20020 | 30000 | 20020 | 60000 | 14166 | 30000 | 0 | 20010 |
| 50025 | 90095 | 44207 | 14177 | 0 | 30030 | 14176 | 0 | 30000 | 42589 | 355405 | 44175 | 20020 | 30000 | 20020 | 60000 | 14166 | 30000 | 0 | 20010 |
| 50024 | 90058 | 44176 | 14176 | 0 | 30000 | 14175 | 0 | 30000 | 42563 | 355293 | 44175 | 20020 | 30000 | 20020 | 60000 | 14166 | 30000 | 0 | 20010 |
| 50024 | 90051 | 44176 | 14176 | 0 | 30000 | 14175 | 0 | 30036 | 35812 | 355677 | 41949 | 20043 | 30036 | 20020 | 60000 | 14166 | 30000 | 0 | 20010 |
| 50024 | 90051 | 44176 | 14176 | 0 | 30000 | 14175 | 0 | 30000 | 42563 | 355291 | 44175 | 20020 | 30000 | 20020 | 60000 | 14166 | 30000 | 0 | 20010 |
| 50024 | 90058 | 44176 | 14176 | 0 | 30000 | 14175 | 0 | 30000 | 42563 | 355287 | 44175 | 20020 | 30000 | 20043 | 60072 | 12368 | 30000 | 0 | 20010 |
| 50024 | 90051 | 44176 | 14176 | 0 | 30000 | 14175 | 0 | 30000 | 42563 | 355287 | 44175 | 20020 | 30000 | 20020 | 60000 | 14166 | 30000 | 0 | 20010 |
| 50024 | 90051 | 44176 | 14176 | 0 | 30000 | 14175 | 0 | 30000 | 42563 | 355290 | 44175 | 20020 | 30000 | 20020 | 60000 | 14166 | 30000 | 0 | 20010 |
| 50024 | 90051 | 44176 | 14176 | 0 | 30000 | 14175 | 0 | 30000 | 42589 | 355400 | 44175 | 20020 | 30000 | 20020 | 60000 | 14166 | 30000 | 0 | 20010 |
Code:
casal w0, w1, [x6]
mov x7, 8
(fused SUBS/B.cc loop)
Result (median cycles for code): 24.0044
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 40208 | 240320 | 33504 | 3434 | 30070 | 1773 | 30036 | 711987 | 2939246 | 33359 | 10212 | 30036 | 10201 | 60006 | 8330 | 30000 | 10100 |
| 40204 | 240044 | 38431 | 8430 | 30001 | 4265 | 30003 | 920650 | 2938456 | 34268 | 10201 | 30003 | 10201 | 60006 | 8330 | 30000 | 10100 |
| 40204 | 240044 | 38431 | 8430 | 30001 | 4265 | 30003 | 920650 | 2938456 | 34268 | 10201 | 30003 | 10212 | 60072 | 5292 | 30000 | 10100 |
| 40204 | 240044 | 38431 | 8430 | 30001 | 4265 | 30003 | 920650 | 2938456 | 34268 | 10201 | 30003 | 10201 | 60006 | 8330 | 30000 | 10100 |
| 40204 | 240044 | 38431 | 8430 | 30001 | 4265 | 30003 | 920650 | 2938456 | 34268 | 10201 | 30003 | 10201 | 60006 | 8330 | 30000 | 10100 |
| 40204 | 240044 | 38431 | 8430 | 30001 | 4265 | 30036 | 410669 | 2938784 | 31994 | 10212 | 30036 | 10201 | 60006 | 8330 | 30000 | 10100 |
| 40204 | 240044 | 38431 | 8430 | 30001 | 4265 | 30003 | 920650 | 2938456 | 34268 | 10201 | 30003 | 10201 | 60006 | 8330 | 30000 | 10100 |
| 40204 | 240044 | 38431 | 8430 | 30001 | 4265 | 30003 | 920650 | 2938456 | 34268 | 10201 | 30003 | 10212 | 60072 | 7405 | 30000 | 10100 |
| 40204 | 240044 | 38431 | 8430 | 30001 | 4265 | 30003 | 920650 | 2938456 | 34268 | 10201 | 30003 | 10201 | 60006 | 8330 | 30000 | 10100 |
| 40204 | 240044 | 38431 | 8430 | 30001 | 4265 | 30003 | 920650 | 2938456 | 34268 | 10201 | 30003 | 10201 | 60006 | 8330 | 30000 | 10100 |
Result (median cycles for code): 24.0044
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 40029 | 240302 | 33420 | 3345 | 0 | 30075 | 1682 | 0 | 30003 | 920388 | 2938548 | 34178 | 10021 | 30003 | 10032 | 60072 | 4411 | 30000 | 10010 |
| 40024 | 240046 | 38339 | 8339 | 0 | 30000 | 4175 | 0 | 30000 | 920370 | 2938443 | 34175 | 10020 | 30000 | 10032 | 60072 | 5316 | 30000 | 10010 |
| 40024 | 240046 | 38339 | 8339 | 0 | 30000 | 4175 | 0 | 30000 | 920367 | 2938430 | 34175 | 10020 | 30000 | 10020 | 60000 | 8329 | 30000 | 10010 |
| 40024 | 240039 | 38339 | 8339 | 0 | 30000 | 4175 | 0 | 30000 | 920367 | 2938430 | 34175 | 10020 | 30000 | 10032 | 60072 | 7639 | 30000 | 10010 |
| 40024 | 240044 | 38339 | 8339 | 0 | 30000 | 4175 | 0 | 30003 | 920380 | 2938546 | 34178 | 10021 | 30003 | 10020 | 60000 | 8330 | 30000 | 10010 |
| 40024 | 240044 | 38340 | 8340 | 0 | 30000 | 4175 | 0 | 30036 | 807304 | 2938886 | 33703 | 10032 | 30036 | 10043 | 60138 | 6383 | 30000 | 10010 |
| 40024 | 240049 | 38340 | 8340 | 0 | 30000 | 4175 | 0 | 30000 | 920380 | 2938529 | 34175 | 10020 | 30000 | 10032 | 60072 | 5011 | 30000 | 10010 |
| 150385 | 604807 | 144712 | 76795 | 1350 | 66567 | 76905 | 1320 | 30036 | 438800 | 2938970 | 32035 | 10032 | 30036 | 10020 | 60000 | 8330 | 30000 | 10010 |
| 40024 | 240044 | 38340 | 8340 | 0 | 30000 | 4175 | 0 | 30000 | 920380 | 2938529 | 34175 | 10020 | 30000 | 10020 | 60000 | 8330 | 30000 | 10010 |
| 40024 | 240044 | 38340 | 8340 | 0 | 30000 | 4175 | 0 | 30036 | 642523 | 2939131 | 32956 | 10032 | 30036 | 10020 | 60000 | 8330 | 30000 | 10010 |