Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
stxr w0, x1, [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0
(no loop instructions)
Retires (minus 70 nops): 1.000
Issues: 1.000
Integer unit issues: 0.001
Load/store unit issues: 1.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) |
| 71005 | 34206 | 1003 | 1 | 1002 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 33866 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 33860 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 33858 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 33860 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 33858 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 33861 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 33858 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 33877 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 33859 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
Code:
stxr w0, x1, [x6] add x6, x6, 8
(fused SUBS/B.cc loop)
Result (median cycles for code): 2.3395
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 20209 | 24098 | 20387 | 10279 | 10108 | 10280 | 10005 | 35493 | 251860 | 20110 | 10205 | 10005 | 10205 | 20010 | 10004 | 10000 | 10100 |
| 20204 | 23398 | 20104 | 10104 | 10000 | 10105 | 10004 | 35473 | 252331 | 20108 | 10204 | 10004 | 10204 | 20008 | 10003 | 10000 | 10100 |
| 20204 | 23399 | 20103 | 10103 | 10000 | 10104 | 10004 | 35473 | 252175 | 20108 | 10204 | 10004 | 10204 | 20008 | 10003 | 10000 | 10100 |
| 20204 | 23394 | 20103 | 10103 | 10000 | 10104 | 10004 | 35473 | 252136 | 20108 | 10204 | 10004 | 10204 | 20008 | 10003 | 10000 | 10100 |
| 20204 | 23405 | 20103 | 10103 | 10000 | 10104 | 10004 | 35473 | 252067 | 20108 | 10204 | 10004 | 10204 | 20008 | 10003 | 10000 | 10100 |
| 20204 | 23406 | 20103 | 10103 | 10000 | 10104 | 10004 | 35473 | 252058 | 20108 | 10204 | 10004 | 10204 | 20008 | 10003 | 10000 | 10100 |
| 20204 | 23386 | 20103 | 10103 | 10000 | 10104 | 10004 | 35473 | 252206 | 20108 | 10204 | 10004 | 10204 | 20008 | 10003 | 10000 | 10100 |
| 20204 | 23418 | 20103 | 10103 | 10000 | 10104 | 10004 | 35473 | 252301 | 20108 | 10204 | 10004 | 10204 | 20008 | 10003 | 10000 | 10100 |
| 20204 | 23310 | 20103 | 10103 | 10000 | 10104 | 10004 | 35473 | 251620 | 20108 | 10204 | 10004 | 10204 | 20008 | 10003 | 10000 | 10100 |
| 20204 | 23415 | 20103 | 10103 | 10000 | 10104 | 10034 | 35809 | 253198 | 20168 | 10234 | 10034 | 10204 | 20008 | 10003 | 10000 | 10100 |
Result (median cycles for code): 2.3899
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 20029 | 25582 | 20241 | 10152 | 10089 | 10157 | 10004 | 35248 | 258495 | 20018 | 10024 | 10004 | 10025 | 20010 | 10004 | 10000 | 10010 |
| 20024 | 23889 | 20011 | 10011 | 10000 | 10010 | 10000 | 35235 | 258724 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
| 20024 | 23937 | 20011 | 10011 | 10000 | 10010 | 10000 | 35235 | 258612 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
| 20024 | 23831 | 20011 | 10011 | 10000 | 10010 | 10000 | 35235 | 258040 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
| 20024 | 23855 | 20011 | 10011 | 10000 | 10010 | 10000 | 35235 | 257644 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
| 20024 | 23784 | 20011 | 10011 | 10000 | 10010 | 10000 | 35235 | 258622 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
| 20024 | 23909 | 20011 | 10011 | 10000 | 10010 | 10000 | 35235 | 258595 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
| 20024 | 23924 | 20011 | 10011 | 10000 | 10010 | 10000 | 35235 | 258783 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
| 20024 | 23904 | 20011 | 10011 | 10000 | 10010 | 10000 | 35235 | 258467 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
| 20024 | 23899 | 20011 | 10011 | 10000 | 10010 | 10000 | 35235 | 258422 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
Code:
stxr w0, x1, [x6]
mov x7, 8
(fused SUBS/B.cc loop)
Result (median cycles for code): 3.0040
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 10205 | 20519 | 10119 | 101 | 10018 | 100 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30040 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528713 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30040 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528713 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30040 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528713 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30040 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528713 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30040 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528713 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30048 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528857 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30040 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528713 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30040 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528713 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30040 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528713 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
Result (median cycles for code): 3.0047
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 10025 | 20160 | 10029 | 11 | 10018 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10025 | 30094 | 10029 | 11 | 10018 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |