Icestorm: CMP (shifted immediate, 64-bit) measurements

Code:

  cmp x0, #3, lsl #12

Initialization

  mov x0, 1

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	512	1001	1001	1000	3000	1000	1000	1000	1001
1004	390	1001	1001	1000	3000	1000	1000	1000	1001
1004	388	1001	1001	1000	3000	1000	1000	1000	1001
1004	391	1001	1001	1000	3000	1000	1000	1000	1001
1004	393	1001	1001	1000	3000	1000	1000	1000	1001
1004	395	1001	1001	1000	3000	1000	1000	1000	1001
1004	392	1001	1001	1000	3000	1000	1000	1000	1001
1004	391	1001	1001	1000	3000	1000	1000	1000	1001
1004	395	1001	1001	1000	3000	1000	1000	1000	1001
1004	391	1001	1001	1000	3000	1000	1000	1000	1001

Test 2: Latency 2->1

Chain cycles: 1

Code:

  cmp x0, #3, lsl #12
  cset x0, cc

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	0	0	20108	0	519434	20107	20212	20212	20001	10100
20204	20030	20101	20101	0	0	20108	0	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	0	0	20108	0	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	0	0	20108	0	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	0	0	20108	0	519548	20108	20216	20255	20015	10100
20204	20030	20101	20101	0	0	20108	0	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	0	0	20108	0	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	0	0	20108	0	519548	20108	20216	20402	20085	10100
20204	20030	20101	20101	0	0	20108	0	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	0	0	20108	0	519548	20108	20216	20216	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519638	20018	20036	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010

Test 3: throughput

Count: 8

Code:

  cmp x0, #3, lsl #12
  cmp x0, #3, lsl #12
  cmp x0, #3, lsl #12
  cmp x0, #3, lsl #12
  cmp x0, #3, lsl #12
  cmp x0, #3, lsl #12
  cmp x0, #3, lsl #12
  cmp x0, #3, lsl #12

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3634

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	29217	80114	80114	80118	240351	80117	80220	80218	80013	100
80204	29119	80113	80113	80118	240357	80119	80220	80220	80012	100
80204	29098	80113	80113	80118	240360	80120	80220	80218	80013	100
80204	29072	80112	80112	80117	240357	80119	80220	80220	80012	100
80204	29075	80115	80115	80119	240360	80120	80220	80220	80013	100
80204	29151	80113	80113	80118	240354	80118	80220	80220	80013	100
80204	29092	80113	80113	80118	240351	80117	80220	80220	80015	100
80204	29049	80113	80113	80118	240357	80119	80220	80220	80015	100
80204	29051	80115	80115	80119	240354	80118	80220	80220	80015	100
80204	29166	80113	80113	80118	240348	80116	80216	80258	80051	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3628

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	30054	80034	80034	80039	240066	80020	80020	80020	80011	10
80024	28996	80021	80021	80020	240068	80020	80020	80020	80011	10
80024	28972	80021	80021	80020	240085	80020	80020	80020	80011	10
80024	29055	80021	80021	80020	240091	80020	80020	80020	80011	10
80024	29086	80021	80021	80020	240088	80020	80020	80020	80011	10
80024	28929	80021	80021	80020	240072	80020	80020	80020	80011	10
80024	28981	80021	80021	80020	240080	80020	80020	80020	80011	10
80024	29054	80021	80021	80020	240071	80020	80020	80020	80011	10
80024	29089	80021	80021	80020	240071	80020	80020	80020	80011	10
80024	28943	80021	80021	80020	240078	80020	80020	80020	80011	10

CMP (shifted immediate, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 2->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations