Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ADR

Test 1: uops

Code:

  adr x0, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 0.500

Integer unit issues: 0.501

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	? int output thing (e9)	? int retires (ef)
1004	532	500	500	499	1497	499	1000	500	1000
1004	291	500	500	499	1500	500	1000	501	1000
1004	280	501	501	500	1500	500	1000	501	1000
1004	280	501	501	500	1500	500	1000	501	1000
1004	280	501	501	500	1500	500	1000	501	1000
1004	289	500	500	499	1500	500	1000	501	1000
1004	280	501	501	500	1500	500	1000	501	1000
1004	280	501	501	500	1500	500	1000	501	1000
1004	280	501	501	500	1500	500	1000	501	1000
1004	280	501	501	500	1500	500	1000	501	1000

Test 2: throughput

Count: 8

Code:

  adr x0, .+4
  adr x1, .+4
  adr x2, .+4
  adr x3, .+4
  adr x4, .+4
  adr x5, .+4
  adr x6, .+4
  adr x7, .+4

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2511

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	20301	40010	40010	40013	0	120039	0	40013	80226	0	200	39910	80100
80204	20096	40010	40010	40013	0	120036	0	40012	80224	0	200	39909	80100
80204	20086	40009	40009	40012	0	120036	0	40012	80224	0	200	39909	80100
80204	20098	40010	40010	40013	0	120036	0	40012	80224	0	200	39909	80100
80204	20086	40009	40009	40012	0	120036	0	40012	80224	0	200	39909	80100
80204	20086	40009	40009	40012	0	120036	0	40012	80224	0	200	39909	80100
80204	20086	40009	40009	40012	0	120036	0	40012	80224	0	200	39909	80100
80204	20086	40009	40009	40012	0	120036	0	40012	80224	0	200	39909	80100
80204	20086	40009	40009	40012	0	120036	0	40012	80224	0	200	39909	80100
80204	20086	40009	40009	40012	0	120036	0	40012	80224	0	200	39909	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2507

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	21998	40022	40022	40025	120097	40025	80050	20	40001	80010
80024	20143	40011	40011	40010	120045	40010	80020	20	40001	80010
80024	20080	40011	40011	40010	120049	40010	80020	20	40001	80010
80024	20058	40011	40011	40010	120049	40010	80020	20	40001	80010
80024	20058	40011	40011	40010	120049	40010	80020	20	40001	80010
80024	20058	40011	40011	40010	120049	40010	80020	20	40038	80010
80024	20107	40011	40011	40010	120045	40010	80020	20	40001	80010
80024	20058	40011	40011	40010	120049	40010	80020	20	40001	80010
80024	20059	40011	40011	40010	120049	40010	80020	20	40001	80010
80024	20058	40011	40011	40010	120049	40010	80020	20	40001	80010