Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

MRS (NZCV)

Test 1: uops

Code:

  mrs x0, nzcv

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	505	1001	1001	1000	3000	1000	1000	1000	1001	1000
1004	371	1001	1001	1000	3000	1000	1000	1000	1001	1000
1004	364	1001	1001	1000	3000	1000	1000	1000	1001	1000
1004	364	1001	1001	1000	3000	1000	1000	1000	1001	1000
1004	364	1001	1001	1000	3000	1000	1000	1000	1001	1000
1004	364	1001	1001	1000	3000	1000	1000	1000	1001	1000
1004	368	1001	1001	1000	3000	1000	1000	1000	1001	1000
1004	364	1001	1001	1000	3000	1000	1000	1000	1001	1000
1004	364	1001	1001	1000	3000	1000	1000	1000	1001	1000
1004	364	1001	1001	1000	3000	1000	1000	1000	1001	1000

Test 2: throughput

Count: 8

Code:

  mrs x0, nzcv
  mrs x1, nzcv
  mrs x2, nzcv
  mrs x3, nzcv
  mrs x4, nzcv
  mrs x5, nzcv
  mrs x6, nzcv
  mrs x7, nzcv

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	26871	80115	80115	80120	292168	80120	80222	80222	80015	80100
80204	26742	80115	80115	80120	293236	80120	80224	80224	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	80281	80059	80100
80204	26737	80115	80115	80120	293236	80120	80224	80222	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	80224	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	80224	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	80224	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	80224	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	80224	80015	80100
80204	26737	80115	80115	80120	293236	80120	80224	80224	80015	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	28001	80038	80038	80051	426780	80020	80020	80020	80011	80010
80024	26792	80021	80021	80020	389437	80020	80020	80020	80011	80010
80024	26722	80021	80021	80020	389437	80020	80020	80020	80011	80010
80024	26722	80021	80021	80020	389437	80020	80020	80020	80011	80010
80024	26722	80021	80021	80020	389437	80020	80020	80020	80011	80010
80024	26722	80021	80021	80020	389437	80020	80020	80020	80011	80010
80024	26722	80021	80021	80020	389437	80020	80020	80020	80011	80010
80024	26722	80021	80021	80020	389437	80020	80020	80020	80011	80010
80024	26722	80021	80021	80020	389437	80020	80020	80020	80011	80010
80024	26722	80021	80021	80020	389437	80020	80020	80020	80011	80010