Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

PRFM (register, PLIL2KEEP)

Test 1: uops

Code:

  prfm plil2keep, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1004	2100	1001	1	1000	1000	35364	1000	1000	1000	1	1000
1004	2117	1001	1	1000	1000	35538	1000	1000	1000	1	1000
1004	2093	1001	1	1000	1000	35068	1000	1000	1000	1	1000
1004	2090	1001	1	1000	1000	35356	1000	1000	1000	1	1000
1004	2074	1001	1	1000	1000	35246	1000	1000	1000	1	1000
1004	2146	1001	1	1000	1000	35084	1000	1000	1000	1	1000
1004	2143	1001	1	1000	1000	35686	1000	1000	1000	1	1000
1004	2143	1001	1	1000	1000	35686	1000	1000	1000	1	1000
1004	2143	1001	1	1000	1000	35686	1000	1000	1000	1	1000
1004	2121	1001	1	1000	1000	35686	1000	1000	1000	1	1000

Test 2: throughput

Code:

  prfm plil2keep, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0067

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20204	20811	20102	10102	10000	10104	10000	61318	349227	20103	10205	10005	10238	10036	10033	10000	10100
20204	20067	20102	10102	10000	10103	10000	61331	348431	20102	10204	10004	10206	10006	10002	10000	10100
20204	20067	20102	10102	10000	10104	10000	61316	349287	20104	10206	10006	10206	10006	10002	10000	10100
20204	20067	20102	10102	10000	10104	10000	61316	349287	20104	10206	10006	10206	10006	10002	10000	10100
20204	20067	20102	10102	10000	10104	10000	61316	349287	20104	10206	10006	10206	10006	10002	10000	10100
20204	20067	20102	10102	10000	10104	10000	61316	349287	20104	10206	10006	10206	10006	10002	10000	10100
20204	20067	20102	10102	10000	10104	10000	61316	349287	20104	10206	10006	10206	10006	10002	10000	10100
20204	20067	20102	10102	10000	10104	10000	61316	349287	20104	10206	10006	10206	10006	10002	10000	10100
20204	20067	20102	10102	10000	10104	10000	61316	349287	20104	10206	10006	10206	10006	10002	10000	10100
20204	20067	20102	10102	10000	10104	10000	61316	349287	20104	10206	10006	10206	10006	10002	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20024	20538	20016	10016	10000	10021	10000	61037	349717	20010	10020	10000	10020	10000	10001	10000	10010
20025	20178	20072	10042	10030	10041	10000	61034	350557	20010	10020	10000	10020	10000	10001	10000	10010
20025	20205	20072	10042	10030	10041	10000	60730	352511	20010	10020	10000	10058	10039	10034	10000	10010
20024	20078	20011	10011	10000	10010	10000	61126	350431	20010	10020	10000	10056	10036	10033	10000	10010
20024	20139	20011	10011	10000	10010	10000	60915	351103	20010	10020	10000	10054	10034	10033	10000	10010
20024	20195	20011	10011	10000	10010	10000	61027	350831	20010	10020	10000	10020	10000	10001	10000	10010
20024	20139	20011	10011	10000	10010	10000	61034	350557	20010	10020	10000	10020	10000	10001	10000	10010
20024	20139	20011	10011	10000	10010	10000	61034	350557	20010	10020	10000	10020	10000	10001	10000	10010
20024	20139	20011	10011	10000	10010	10000	60319	350427	20010	10020	10000	10020	10000	10001	10000	10010
20024	20195	20011	10011	10000	10010	10000	61034	350557	20010	10020	10000	10020	10000	10001	10000	10010

Test 3: throughput

Code:

  prfm plil2keep, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0503

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10204	20509	10101	101	10000	100	10002	300	357182	10102	200	10012	200	10012	1	10000	100
10204	20505	10101	101	10000	100	10000	300	357254	10100	200	10004	200	10004	1	10000	100
10204	20503	10101	101	10000	100	10000	300	357200	10100	200	10004	200	10008	1	10000	100
10204	20483	10101	101	10000	100	10000	300	357234	10100	200	10004	200	10008	1	10000	100
10204	20478	10101	101	10000	100	10004	300	357102	10104	200	10012	200	10008	1	10000	100
10204	20501	10101	101	10000	100	10000	300	357310	10100	200	10004	200	10012	1	10000	100
10204	20475	10101	101	10000	100	10002	300	357198	10102	200	10012	200	10004	1	10000	100
10204	20470	10101	101	10000	100	10000	300	357392	10100	200	10008	200	10012	1	10000	100
10204	20515	10101	101	10000	100	10000	300	357168	10100	200	10004	200	10004	1	10000	100
10204	20475	10101	101	10000	100	10144	313	363787	10248	204	10172	200	10008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0888

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10024	20061	10011	11	10000	10	10002	30	349144	10012	20	10012	20	10000	1	10000	10
10024	19995	10011	11	10000	10	10000	30	349136	10010	20	10000	20	10000	1	10000	10
10024	20058	10011	11	10000	10	10000	30	349136	10010	20	10000	20	10000	1	10000	10
10024	20058	10011	11	10000	10	10000	30	349136	10010	20	10000	20	10000	1	10000	10
10024	20058	10011	11	10000	10	10000	30	349136	10010	20	10000	20	10000	1	10000	10
10024	20058	10011	11	10000	10	10000	30	349136	10010	20	10000	20	10000	1	10000	10
10024	20058	10011	11	10000	10	10000	30	349136	10010	20	10000	20	10000	1	10000	10
10024	19966	10011	11	10000	10	10000	30	347048	10010	20	10000	20	10010	1	10000	10
10024	20708	10011	11	10000	10	10000	30	355448	10010	20	10000	20	10000	1	10000	10
10024	20958	10011	11	10000	10	10000	30	365426	10010	20	10000	20	10000	1	10000	10