Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDR (register, 64-bit)

Test 1: uops

Code:

  ldr x0, [x6, x7]
  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
10056521029110281000823810001000200011000
10045541001110001000823810001000200011000
10045541001110001000823810001000200011000
10045541001110001000823810001000200011000
10045541001110001000823810001000200011000
10045541001110001000823810001000200011000
10045541001110001000823810001000200011000
10045541001110001000823810001000200011000
10045541001110001000823810001000200011000
10045541001110001000823810001000200011000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldr x0, [x6, x7]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4020570155401083010710001301301000318592966938064010630210100046022420008300021000030100
4020470040401023010210000301031000318593926939934010630212100046022420008300021000030100
4020570077401113010910002301351000318596356940924010630212100046022420008300021000030100
4020470040401023010210000301031000318593926939934010630212100046022420008300021000030100
4020470040401023010210000301031000318593926939934010630212100046022420008300021000030100
4020470040401023010210000301031000318593926939934010630212100046022420008300021000030100
4020470040401023010210000301031000318593926939934010630212100046022420008300021000030100
4020470040401023010210000301031000318593926939934010630212100046022420008300021000030100
4020470040401023010210000301031000318593926939934010630212100046022420008300021000030100
4020470042401023010210000301031000318595816940704010630212100046029420034300111000030100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
40025701614001830017100013004010003185962369369640016300301000460020200003000310000030010
40024700474001330013100003001010000185946369464440010300201000060020200003000310000030010
40024700404001230012100003001010000185946369464440010300201000060020200003000310000030010
40024700404001230012100003001010000185946369464440010300201000060020200003000210000030010
40024700404001230012100003001010000185946369464440010300201000060020200003000210000030010
40024700404001230012100003001010000185946369464440010300201000060020200003000210000030010
40024700404001230012100003001010000185946369464440010300201000060020200003000210000030010
40025700704002030018100023004510000185992269483140010300201000060020200003000210000030010
40024700404001230012100003001010000185946369464440010300201000060020200003000210000030010
40024700404001230012100003001010000185946369464440010300201000060020200003000210000030010

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldr x0, [x6, x7]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8
  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4020570148401083010710001301301000318594856938764010630210100046029420034300091000030100
4020470053401023010210000301031000318595336939214010630210100046022420008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100
4020470040401023010210000301031000318595816940634010630212100046022420008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4002570437400183001710001300401000318596776937164001630030100046002020000300031000030010
4002470049400133001310000300101000018597066947344001030020100006002020000300031000030010
4002470042400123001210000300101000018597066947344001030020100006002020000300031000030010
4002470042400123001210000300101000018597066947344001030020100006002020000300031000030010
4002470042400123001210000300101000018597066947344001030020100006002020000300031000030010
4002470042400123001210000300101000018597066947344001030020100006002020000300031000030010
4002470114400123001210000300101000318596716947384001630032100046011820034300091000030010
4002470058400123001210000300131000018597876947684001030020100006002020000300031000030010
4002470041400123001210000300101000018596526947144001030020100006002020000300031000030010
4002470040400123001210000300101000018596526947144001030020100006002020000300031000030010

Test 4: throughput

Count: 8

Code:

  ldr x0, [x6, x7]
  ldr x0, [x6, x7]
  ldr x0, [x6, x7]
  ldr x0, [x6, x7]
  ldr x0, [x6, x7]
  ldr x0, [x6, x7]
  ldr x0, [x6, x7]
  ldr x0, [x6, x7]
  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
80205401548012310180022100800083002561908010820080012200160024180000100
80204400538010110180000100800083006400708010820080012200160024180000100
80204400458010110180000100800083006400708010820080012200160024180000100
80204400458010110180000100800083006400708010820080012200160028180000100
80204400458010110180000100800083006400708010820080012200160024180000100
80204400458010110180000100800083006400708010820080012200160024180000100
80204400458010110180000100800083006400708010820080012200160142180000100
80204400488010110180000100800083006400708010820080012200160024180000100
80204400458010110180000100800083006400708010820080012200160024180000100
80204400458010110180000100800083006400708010820080012200160024180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
80025403268004311800321080000306400408001020800002016000018000010
80024400438001111800001080000306400408001020800002016000018000010
80024400438001111800001080000306400408001020800002016000018000010
80024400438001111800001080056303503568006620800692016000018000010
80024400438001111800001080000306400408001020800002016000018000010
80024400438001111800001080000306401668001020800002016000018000010
80024400598001111800001080000306400408001020800002016000018000010
80024400438001111800001080000306400408001020800002016000018000010
80024400438001111800001080000306400408001020800002016000018000010
80024400508001111800001080000306419848001020800002016000018000010