Icestorm: BFXIL (32-bit) measurements

Code:

  bfxil w0, w1, #3, #7

Initialization

  mov x0, 1

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	1030	1001	1001	1000	3000	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	3000	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	3000	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	3000	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	3000	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	3000	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	3000	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	3000	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	3000	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	3000	1000	1000	2000	1001	1000

Test 2: Latency 1->1

Code:

  bfxil w0, w1, #3, #7

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0034

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10054	10104	10104	0	10105	30315	10105	10212	20224	10004	10100
10204	10034	10104	10104	0	10105	30315	10105	10212	20224	10004	10100
10204	10034	10104	10104	0	10105	30315	10105	10212	20224	10004	10100
10204	10034	10104	10104	0	10105	30315	10105	10212	20224	10004	10100
10204	10034	10104	10104	0	10105	30315	10105	10212	20224	10004	10100
10204	10034	10104	10104	0	10105	30315	10105	10212	20224	10004	10100
10204	10034	10104	10104	0	10105	30315	10105	10212	20224	10004	10100
10204	10034	10104	10104	0	10105	30315	10105	10212	20224	10004	10100
10204	10034	10104	10104	0	10105	30315	10105	10212	20224	10004	10100
10204	10034	10104	10104	0	10105	30315	10105	10212	20224	10004	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10035	10025	10025	10026	30060	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	30060	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	30060	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	30060	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	30060	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	30060	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	30060	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	30060	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	30060	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	30060	10020	10020	20020	10011	10010

Test 3: Latency 1->2

Chain cycles: 1

Code:

  add x1, x0, x0
  mov x0, 0
  bfxil w0, w1, #3, #7

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30204	20033	20201	20201	20208	0	380030	0	0	20207	20213	0	0	40226	20101	30100
30204	20030	20201	20201	20207	0	380324	0	0	20208	20213	0	0	40226	20101	30100
30204	20030	20201	20201	20208	0	380324	0	0	20208	20213	0	0	40226	20101	30100
30204	20030	20201	20201	20208	0	380324	0	0	20208	20213	0	0	40226	20101	30100
30204	20241	20285	20285	20356	0	380324	0	0	20208	20213	0	0	40226	20101	30100
30204	20030	20201	20201	20208	0	380324	0	0	20208	20213	0	0	40226	20101	30100
30204	20030	20201	20201	20208	0	380324	0	0	20208	20213	0	0	40226	20101	30100
30204	20030	20201	20201	20208	0	380324	0	0	20208	20213	0	0	40226	20101	30100
30204	20030	20201	20201	20208	0	380324	0	0	20208	20213	0	0	40226	20101	30100
30204	20030	20201	20201	20208	0	380324	0	0	20208	20213	0	0	40226	20101	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30024	20032	20011	20011	0	20015	379685	20010	20020	40020	20001	30010
30025	20060	20025	20025	0	20048	379684	20010	20020	40020	20001	30010
30024	20030	20011	20011	0	20010	379776	20010	20020	40020	20001	30010
30024	20030	20011	20011	0	20010	379776	20010	20020	40020	20001	30010
30024	20030	20011	20011	0	20010	379776	20010	20020	40020	20001	30010
30024	20030	20011	20011	0	20010	379776	20010	20020	40020	20001	30010
30024	20030	20011	20011	0	20010	379776	20010	20020	40020	20001	30010
30024	20030	20011	20011	0	20010	379776	20010	20020	40020	20001	30010
30024	20030	20011	20011	0	20010	379776	20010	20020	40020	20001	30010
30024	20030	20011	20011	0	20010	379776	20010	20020	40020	20001	30010

Test 4: throughput

Count: 8

Code:

  bfxil w0, w8, #3, #7
  bfxil w1, w8, #3, #7
  bfxil w2, w8, #3, #7
  bfxil w3, w8, #3, #7
  bfxil w4, w8, #3, #7
  bfxil w5, w8, #3, #7
  bfxil w6, w8, #3, #7
  bfxil w7, w8, #3, #7

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	80054	80104	80104	80105	0	240315	0	0	80105	80210	0	0	160224	80004	80100
80204	80034	80104	80104	80105	0	240315	0	0	80105	80212	0	0	160224	80004	80100
80204	80034	80104	80104	80105	0	240315	0	0	80105	80212	0	0	160224	80004	80100
80204	80034	80104	80104	80105	0	240315	0	0	80105	80212	0	0	160224	80004	80100
80204	80034	80104	80104	80105	0	240315	0	0	80105	80212	0	0	160224	80004	80100
80205	80064	80118	80118	80122	0	240315	0	0	80105	80212	0	0	160224	80004	80100
80204	80034	80104	80104	80105	0	240315	0	0	80105	80212	0	0	160224	80004	80100
80204	80034	80104	80104	80105	0	240315	0	0	80105	80212	0	0	160224	80004	80100
80204	80034	80104	80104	80105	0	240315	0	0	80105	80212	0	0	160224	80004	80100
80204	80034	80104	80104	80105	0	240315	0	0	80105	80212	0	0	160224	80004	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	80035	80025	80025	80026	240060	80020	80020	160020	80011	80010
80024	80030	80021	80021	80020	240060	80020	80020	160020	80011	80010
80024	80030	80021	80021	80020	240060	80020	80020	160092	80029	80010
80024	80030	80021	80021	80020	240060	80020	80020	160020	80011	80010
80024	80030	80021	80021	80020	240060	80020	80020	160020	80011	80010
80024	80030	80021	80021	80020	240060	80020	80020	160020	80011	80010
80024	80030	80021	80021	80020	240060	80020	80020	160020	80011	80010
80024	80030	80021	80021	80020	240060	80020	80020	160020	80011	80010
80024	80030	80021	80021	80020	240060	80020	80020	160020	80011	80010
80024	80030	80021	80021	80020	240060	80020	80020	160092	80029	80010

BFXIL (32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations