Icestorm: LDRSH (post-index, 32-bit) measurements

Code:

  ldrsh w0, [x6], #8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
2005	1382	2039	1020	1019	1042	1000	21093	17838	2000	1000	1000	1000	1000	1001	1000	1000
2004	1071	2001	1001	1000	1000	1000	20882	18254	2000	1000	1000	1000	1000	1001	1000	1000
2004	1068	2001	1001	1000	1000	1000	21373	17755	2000	1000	1000	1000	1000	1001	1000	1000
2004	1081	2001	1001	1000	1000	1000	21339	17786	2000	1000	1000	1000	1000	1001	1000	1000
2004	1084	2001	1001	1000	1000	1000	21392	17682	2000	1000	1000	1000	1000	1001	1000	1000
2004	1082	2001	1001	1000	1000	1000	21272	17719	2000	1000	1000	1000	1000	1001	1000	1000
2004	1080	2001	1001	1000	1000	1000	21347	17715	2000	1000	1000	1000	1000	1001	1000	1000
2004	1080	2001	1001	1000	1000	1000	21347	17733	2000	1000	1000	1000	1000	1001	1000	1000
2004	1083	2001	1001	1000	1000	1000	21640	17668	2000	1000	1000	1000	1000	1001	1000	1000
2004	1083	2001	1001	1000	1000	1000	21399	17720	2000	1000	1000	1000	1000	1001	1000	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh w0, [x6], #8
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0115

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50209	71088	50158	40153	10005	40247	10003	1851608	535102	50109	40212	10004	70221	10004	40004	10000	40100
50204	70117	50104	40104	10000	40106	10003	1850528	534766	50109	40212	10004	70221	10004	40004	10000	40100
50204	70115	50104	40104	10000	40106	10003	1850604	534822	50109	40212	10004	70221	10004	40004	10000	40100
50204	70115	50104	40104	10000	40106	10003	1850604	534822	50109	40212	10004	70221	10004	40004	10000	40100
50204	70115	50104	40104	10000	40106	10003	1850604	534822	50109	40212	10004	70221	10004	40004	10000	40100
50205	70194	50117	40115	10002	40140	10003	1851117	534987	50109	40212	10004	70221	10004	40004	10000	40100
50204	70115	50104	40104	10000	40106	10003	1850550	534806	50109	40212	10004	70221	10004	40004	10000	40100
50204	70115	50104	40104	10000	40106	10003	1850604	534822	50109	40212	10004	70221	10004	40004	10000	40100
50204	70115	50104	40104	10000	40106	10003	1851063	534963	50109	40212	10004	70221	10004	40004	10000	40100
50204	70115	50104	40104	10000	40106	10003	1850604	534822	50109	40212	10004	70221	10004	40004	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0104

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50029	71631	50069	40064	10005	40156	10003	1850672	535101	50019	40032	10004	70020	10000	40004	10000	40010
50024	70115	50014	40014	10000	40010	10013	1851914	535542	50061	40073	10015	70020	10000	40004	10000	40010
50024	70104	50013	40013	10000	40010	10000	1850363	535070	50010	40020	10000	70020	10000	40003	10000	40010
50024	70104	50013	40013	10000	40010	10000	1850363	535070	50010	40020	10000	70020	10000	40003	10000	40010
50024	70104	50013	40013	10000	40010	10000	1850363	535070	50010	40020	10000	70020	10000	40003	10000	40010
50024	70104	50013	40013	10000	40010	10000	1850363	535070	50010	40020	10000	70020	10000	40003	10000	40010
50024	70104	50013	40013	10000	40010	10000	1850363	535070	50010	40020	10000	70020	10000	40003	10000	40010
50024	70104	50013	40013	10000	40010	10000	1850363	535070	50010	40020	10000	70020	10000	40003	10000	40010
50024	70104	50013	40013	10000	40010	10000	1850363	535070	50010	40020	10000	70020	10000	40003	10000	40010
50025	70220	50026	40024	10002	40050	10000	1851173	535317	50010	40020	10000	70020	10000	40003	10000	40010

Test 3: throughput

Count: 8

Code:

  ldrsh w0, [x6], #8
  ldrsh w0, [x7], #8
  ldrsh w0, [x8], #8
  ldrsh w0, [x9], #8
  ldrsh w0, [x10], #8
  ldrsh w0, [x11], #8
  ldrsh w0, [x12], #8
  ldrsh w0, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5409

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160209	44402	160411	80313	80098	80316	80012	240578	639644	160124	80212	80012	80212	80012	80009	80000	80100
160204	43229	160112	80109	80003	80112	80009	240485	628797	160121	80212	80012	80212	80012	80009	80000	80100
160204	43220	160109	80109	80000	80112	80010	240485	642470	160122	80212	80012	80212	80012	80009	80000	80100
160204	43217	160109	80109	80000	80112	80008	240473	636092	160116	80208	80008	80212	80012	80009	80000	80100
160204	43218	160109	80109	80000	80112	80012	240485	643383	160124	80212	80012	80212	80012	80009	80000	80100
160204	43217	160109	80109	80000	80112	80012	240485	642122	160124	80212	80012	80212	80012	80009	80000	80100
160205	43325	160179	80149	80030	80150	80009	240485	641036	160121	80212	80012	80212	80012	80009	80000	80100
160204	43217	160109	80109	80000	80112	80009	240485	635285	160121	80212	80012	80254	80054	80051	80000	80100
160204	43216	160109	80109	80000	80112	80012	240485	644224	160124	80212	80012	80208	80008	80007	80000	80100
160204	43217	160109	80109	80000	80112	80010	240485	645802	160122	80212	80012	80212	80012	80009	80000	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5405

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160029	44337	160332	80221	80111	80222	80054	240927	621193	160118	80074	80054	80032	80012	80009	80000	80010
160024	43245	160019	80019	80000	80022	80010	240530	642972	160032	80032	80012	80020	80000	80001	80000	80010
160024	43244	160011	80011	80000	80010	80000	240509	642006	160010	80020	80000	80020	80000	80001	80000	80010
160024	43244	160011	80011	80000	80010	80000	240479	643235	160010	80020	80000	80020	80000	80001	80000	80010
160024	43244	160011	80011	80000	80010	80000	240517	640973	160010	80020	80000	80020	80000	80001	80000	80010
160024	43246	160011	80011	80000	80010	80000	240514	642604	160010	80020	80000	80020	80000	80001	80000	80010
160024	43255	160011	80011	80000	80010	80000	240518	642056	160010	80020	80000	80020	80000	80001	80000	80010
160024	43244	160011	80011	80000	80010	80000	240490	643475	160010	80020	80000	80020	80000	80001	80000	80010
160024	43244	160011	80011	80000	80010	80000	240504	642175	160010	80020	80000	80020	80000	80001	80000	80010
160024	43244	160011	80011	80000	80010	80000	240504	643090	160010	80020	80000	80020	80000	80001	80000	80010

LDRSH (post-index, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations