Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

MOVZ (32-bit)

Test 1: uops

Code:

  movz w0, #0x1234, lsl 16
  nop ; nop ; nop

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 3 nops): 1.000

Issues: 0.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)map int uop (7c)? int output thing (e9)? int retires (ef)
4004192211100011000
4004106911100011000
4004102511100011000
4004102511100011000
4004102511100011000
4004102511100011000
4004102511100011000
4004102511100011000
4004102511100011000
4004104311100011000

Test 2: throughput

Count: 8

Code:

  movz w0, #0x1234, lsl 16
  movz w1, #0x1234, lsl 16
  movz w2, #0x1234, lsl 16
  movz w3, #0x1234, lsl 16
  movz w4, #0x1234, lsl 16
  movz w5, #0x1234, lsl 16
  movz w6, #0x1234, lsl 16
  movz w7, #0x1234, lsl 16

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2511

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
802042026840010400104001312003940013802262003991080100
802042010940010400104001312004240014802262003990980100
802042008640009400094001212003640012802242003990980100
802042008640009400094001212003640012802242003990980100
802042008640009400094001212003640012802242003990980100
802042008640009400094001212003640012802242003990980100
802042008640009400094001212003640012802242003990980100
802042008640009400094001212003640012802242003990980100
802042008640009400094001212003640012802242003990980100
802042008640009400094001212003640012802242003990980100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2507

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
80024219794002140021400241200844002380047204000280010
80024201684001140011400101200494001080020204000180010
80024200694001140011400101201854005780118204000180010
80024200874001140011400101200494001080020204000180010
80024200584001140011400101200494001080020204000180010
80024200584001140011400101200494001080020204000180010
80024200694001140011400101200494001080020204000180010
80024200584001140011400101200494001080020204000180010
80024200584001140011400101200494001080020204000180010
80024200584001140011400101200494001080020204000180010