Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

TST (immediate, 64-bit)

Test 1: uops

Code:

  tst x0, #3

Initialization

  mov x0, 1

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	525	1001	1001	1000	3000	1000	1000	1000	1001
1004	391	1001	1001	1000	3000	1000	1000	1000	1001
1004	392	1001	1001	1000	3000	1000	1000	1000	1001
1004	392	1001	1001	1000	3000	1000	1000	1000	1001
1004	396	1001	1001	1000	3000	1000	1000	1000	1001
1004	391	1001	1001	1000	3000	1000	1000	1000	1001
1004	390	1001	1001	1000	3000	1000	1000	1000	1001
1004	391	1001	1001	1000	3000	1000	1000	1000	1001
1004	392	1001	1001	1000	3000	1000	1000	1000	1001
1004	395	1001	1001	1000	3000	1000	1000	1000	1001

Test 2: Latency 2->1

Chain cycles: 1

Code:

  tst x0, #3
  cset x0, cc

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20108	519318	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519495	20018	20036	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519924	20057	20077	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010

Test 3: throughput

Count: 8

Code:

  tst x0, #3
  tst x0, #3
  tst x0, #3
  tst x0, #3
  tst x0, #3
  tst x0, #3
  tst x0, #3
  tst x0, #3

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3635

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	29176	80115	80115	80119	240351	80117	80220	80218	80013	100
80204	29057	80114	80114	80118	240351	80117	80220	80220	80013	100
80204	29075	80112	80112	80117	240354	80118	80220	80220	80015	100
80204	29077	80113	80113	80118	240357	80119	80220	80220	80013	100
80204	29067	80115	80115	80119	240354	80118	80220	80220	80013	100
80204	29164	80114	80114	80118	240354	80118	80220	80220	80012	100
80204	29066	80115	80115	80119	240354	80118	80220	80220	80012	100
80204	29166	80113	80113	80118	240357	80119	80220	80220	80012	100
80204	29085	80112	80112	80117	240354	80118	80220	80220	80015	100
80204	29058	80115	80115	80120	240357	80119	80220	80220	80015	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3630

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	30144	80035	80035	0	0	80039	0	240137	80041	80042	80020	80011	10
80024	28998	80021	80021	0	0	80020	0	240096	80020	80020	80020	80011	10
80024	29132	80021	80021	0	0	80020	0	240069	80020	80020	80020	80011	10
80024	29038	80021	80021	0	0	80020	0	240084	80020	80020	80020	80011	10
80024	28929	80021	80021	0	0	80020	0	240069	80020	80020	80020	80011	10
80024	29083	80021	80021	0	0	80020	0	240069	80020	80020	80020	80011	10
80024	29042	80021	80021	0	0	80020	0	240077	80020	80020	80020	80011	10
80024	28964	80021	80021	0	0	80020	0	240068	80020	80020	80020	80011	10
80024	28956	80021	80021	0	0	80020	0	240086	80020	80020	80020	80011	10
80024	28931	80021	80021	0	0	80020	0	240100	80020	80020	80020	80011	10