Icestorm: LDUR (64-bit) measurements

Code:

  ldur x0, [x6, #1]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1159	1031	1	1030	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	549	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	1000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldur x0, [x6, #1]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70150	40108	30107	0	10001	30130	0	10003	1859344	693948	40106	30212	10004	60224	10004	30002	10000	30100
40204	70040	40102	30102	0	10000	30103	0	10003	1859392	693993	40106	30212	10004	60224	10004	30002	10000	30100
40204	70049	40103	30103	0	10000	30103	0	10003	1859398	693968	40106	30212	10004	60224	10004	30002	10000	30100
40204	70042	40102	30102	0	10000	30103	0	10003	1859446	694013	40106	30212	10004	60294	10017	30009	10000	30100
40204	70042	40102	30102	0	10000	30103	0	10003	1859446	694013	40106	30212	10004	60224	10004	30002	10000	30100
40204	70042	40102	30102	0	10000	30103	0	10003	1859635	694086	40106	30212	10004	60224	10004	30002	10000	30100
40204	70042	40102	30102	0	10000	30103	0	10003	1859446	694013	40106	30212	10004	60224	10004	30002	10000	30100
40204	70042	40102	30102	0	10000	30103	0	10003	1859446	694013	40106	30212	10004	60224	10004	30002	10000	30100
40204	70042	40102	30102	0	10000	30103	0	10003	1859446	694013	40106	30212	10004	60302	10017	30008	10000	30100
40204	70042	40102	30102	0	10000	30103	0	10003	1859446	694013	40106	30212	10004	60224	10004	30002	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70381	40018	30017	10001	30040	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	30010
40025	70079	40021	30019	10002	30045	10000	1859658	693674	40010	30020	10000	60020	10000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	30010
40024	70113	40013	30013	10000	30010	10000	1859922	694822	40010	30020	10000	60020	10000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	30010
40024	70052	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60114	10017	30009	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	10000	30003	10000	30010

Test 3: throughput

Count: 8

Code:

  ldur x0, [x6, #1]
  ldur x0, [x6, #1]
  ldur x0, [x6, #1]
  ldur x0, [x6, #1]
  ldur x0, [x6, #1]
  ldur x0, [x6, #1]
  ldur x0, [x6, #1]
  ldur x0, [x6, #1]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40175	80127	101	80026	100	80008	300	256190	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80008	300	640070	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	642320	80108	200	80012	200	80012	1	80000	100
80204	40061	80101	101	80000	100	80008	300	640214	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	80012	1	80000	100
80205	40098	80138	101	80037	100	80008	300	640070	80108	200	80012	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40325	80035	11	80024	10	80008	30	259318	80018	20	80012	20	80012	1	80000	10
80024	40054	80015	11	80004	10	80000	30	640166	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	80000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640166	80010	20	80000	20	80000	1	80000	10

LDUR (64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations