Icestorm: LDRSH (register, lsl, 64-bit) measurements

Code:

  ldrsh x0, [x6, x7, lsl #1]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	659	1029	1	1028	1000	8238	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8238	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	2000	1	1000
1004	565	1001	1	1000	1000	8274	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8292	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8130	1000	1000	2000	1	1000
1004	555	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	2000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh x0, [x6, x7, lsl #1]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70486	40108	30107	10001	30130	10003	1859296	693806	40106	30210	10004	60224	20008	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60302	20034	30008	10000	30100
40204	70068	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70066	40102	30102	10000	30103	10003	1859851	694180	40106	30212	10004	60224	20008	30002	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70159	40018	30017	10001	30040	10000	1859658	693674	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70063	40013	30013	10000	30010	10015	1862041	705811	40060	30068	10017	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10027	1863223	695139	40104	30108	10030	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70056	40013	30013	10000	30010	10000	1859733	694745	40010	30020	10000	60020	20000	30003	10000	30010
40025	70173	40021	30019	10002	30045	10000	1859787	694767	40010	30020	10000	60044	20010	30003	10000	30010
40024	70047	40013	30013	10000	30013	10015	1861987	695648	40060	30071	10017	60020	20000	30003	10000	30010
40025	70091	40021	30019	10002	30045	10000	1859868	694802	40010	30020	10000	60020	20000	30003	10000	30010

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh x0, [x6, x7, lsl #1]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70153	40108	30107	10001	30130	10003	1859491	693736	40106	30210	10004	60224	20008	30003	10000	30100
40205	70079	40111	30109	10002	30135	10003	1860256	694336	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10015	1859881	694191	40152	30251	10017	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70161	40018	30017	10001	30040	10012	1859980	693781	40054	30059	10013	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70072	40013	30013	10000	30010	10000	1859733	694745	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859787	694767	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40025	70079	40021	30019	10002	30045	10000	1859760	694756	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010

Test 4: throughput

Count: 8

Code:

  ldrsh x0, [x6, x7, lsl #1]
  ldrsh x0, [x6, x7, lsl #1]
  ldrsh x0, [x6, x7, lsl #1]
  ldrsh x0, [x6, x7, lsl #1]
  ldrsh x0, [x6, x7, lsl #1]
  ldrsh x0, [x6, x7, lsl #1]
  ldrsh x0, [x6, x7, lsl #1]
  ldrsh x0, [x6, x7, lsl #1]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40368	80137	101	80036	100	80008	300	248262	80108	200	80012	200	160024	1	80000	100
80204	40057	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80205	40106	80131	101	80030	100	80057	300	641715	80157	200	80069	200	160028	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40251	80037	11	80026	10	80008	30	320190	0	80018	20	80012	0	20	160000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640040	0	80010	20	80000	0	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	0	80010	20	80000	0	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	0	80010	20	80000	0	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	0	80010	20	80000	0	20	160138	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	0	80010	20	80000	0	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	0	80010	20	80000	0	20	160138	1	80000	10
80024	40124	80011	11	80000	10	80000	30	640130	0	80010	20	80000	0	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	0	80010	20	80000	0	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	0	80010	20	80000	0	20	160000	1	80000	10

LDRSH (register, lsl, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations