Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

MVN (register, ror, 32-bit)

Test 1: uops

Code:

  mvn w0, w0, ror #17
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
100420302001200110005226510001000100020011000
100420302001200110005226510001000100020011000
100420302001200110005226510001000100020011000
100420302001200110005226510001000100020011000
100420302001200110005226510001000100020011000
100420302001200110005226510001000100020011000
100420302001200110005226510001000100020011000
100420302001200110005226510001000100020011000
100420302001200110005226510001000100020011000
100420302001200110005226510001000100020011000

Test 2: Latency 1->2

Code:

  mvn w0, w0, ror #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204200302010120101001010400529100010104102100102122000110100
10204200302010120101001010400529186010104102120102522001510100
10204200302010120101001010400529186010104102120102132000110100
2795047363353372871271655418223720529143010104102100102122000110100
10204200302010120101001010400529143010104102100102102000110100
10204200302010120101001010400529186010104102120102122000110100
10205200602011520115001013700529186010104102120102122000110100
10204200302010120101001010400529186010104102120102122000110100
10204200302010120101001010400529186010104102120102122000110100
10204200302010120101001010400529186010104102120102122000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024200302002120021100255292211002510034100202001110010
10024200302002120021100205292531002010020100202001110010
10024200302002120021100205292531002010020100202001110010
10024200302002120021100205292531002010020100202001110010
10024200302002120021100205292531002010020100202001110010
10024200302002120021100205292531002010020100202001110010
10024200302002120021100205292531002010020100202001110010
10024200302002120021100205292531002010020100202001110010
10024200302002120021100205292531002010020100202001110010
10024200302002120021100205292531002010020100202001110010

Test 3: throughput

Count: 8

Code:

  mvn w0, w8, ror #17
  mvn w1, w8, ror #17
  mvn w2, w8, ror #17
  mvn w3, w8, ror #17
  mvn w4, w8, ror #17
  mvn w5, w8, ror #17
  mvn w6, w8, ror #17
  mvn w7, w8, ror #17
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
802045342916011816011880131136030180130802368023616001780100
802045340416011716011780130136056680130802368023616001780100
802045340416011716011780130136083880130802368023616001780100
802045340416011716011780130136083880130802368023616001780100
802045340416011716011780130136083880130802368023616001780100
802045340416011716011780130136083880130802368023616001780100
802055343316015916015980175136114780176802898023616001780100
802045340416011716011780130136083880130802368023616001780100
621934145012420712420762187136083880130802368023616001780100
802045340416011716011780130136083880130802368023616001780100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6671

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
800245337816003916003980051135997580051800568002016001180010
800245337116002116002180020135990380020800208002016001180010
800245337116002116002180020135990380020800208002016001180010
800245337116002116002180020135990380020800208002016001180010
800245337116002116002180020135990380020800208023016027180010
800245337116002116002180020135990380020800208002016001180010
800245337116002116002180020135990380020800208002016001180010
800245337116002116002180020135990380020800208002016001180010
800245337116002116002180020135990380020800208002016001180010
800245337116002116002180020136106780225802258002016001180010