Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
mvn w0, w0, ror #17
mov x0, 1 mov x1, 2
(no loop instructions)
Retires: 1.000
Issues: 2.000
Integer unit issues: 2.001
Load/store unit issues: 0.000
SIMD/FP unit issues: 0.000
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
1004 | 2030 | 2001 | 2001 | 1000 | 52265 | 1000 | 1000 | 1000 | 2001 | 1000 |
1004 | 2030 | 2001 | 2001 | 1000 | 52265 | 1000 | 1000 | 1000 | 2001 | 1000 |
1004 | 2030 | 2001 | 2001 | 1000 | 52265 | 1000 | 1000 | 1000 | 2001 | 1000 |
1004 | 2030 | 2001 | 2001 | 1000 | 52265 | 1000 | 1000 | 1000 | 2001 | 1000 |
1004 | 2030 | 2001 | 2001 | 1000 | 52265 | 1000 | 1000 | 1000 | 2001 | 1000 |
1004 | 2030 | 2001 | 2001 | 1000 | 52265 | 1000 | 1000 | 1000 | 2001 | 1000 |
1004 | 2030 | 2001 | 2001 | 1000 | 52265 | 1000 | 1000 | 1000 | 2001 | 1000 |
1004 | 2030 | 2001 | 2001 | 1000 | 52265 | 1000 | 1000 | 1000 | 2001 | 1000 |
1004 | 2030 | 2001 | 2001 | 1000 | 52265 | 1000 | 1000 | 1000 | 2001 | 1000 |
1004 | 2030 | 2001 | 2001 | 1000 | 52265 | 1000 | 1000 | 1000 | 2001 | 1000 |
Code:
mvn w0, w0, ror #17
mov x0, 1 mov x1, 2
(fused SUBS/B.cc loop)
Result (median cycles for code): 2.0030
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
10204 | 20030 | 20101 | 20101 | 0 | 0 | 10104 | 0 | 0 | 529100 | 0 | 10104 | 10210 | 0 | 10212 | 20001 | 10100 |
10204 | 20030 | 20101 | 20101 | 0 | 0 | 10104 | 0 | 0 | 529186 | 0 | 10104 | 10212 | 0 | 10252 | 20015 | 10100 |
10204 | 20030 | 20101 | 20101 | 0 | 0 | 10104 | 0 | 0 | 529186 | 0 | 10104 | 10212 | 0 | 10213 | 20001 | 10100 |
27950 | 47363 | 35337 | 28712 | 71 | 6554 | 18223 | 72 | 0 | 529143 | 0 | 10104 | 10210 | 0 | 10212 | 20001 | 10100 |
10204 | 20030 | 20101 | 20101 | 0 | 0 | 10104 | 0 | 0 | 529143 | 0 | 10104 | 10210 | 0 | 10210 | 20001 | 10100 |
10204 | 20030 | 20101 | 20101 | 0 | 0 | 10104 | 0 | 0 | 529186 | 0 | 10104 | 10212 | 0 | 10212 | 20001 | 10100 |
10205 | 20060 | 20115 | 20115 | 0 | 0 | 10137 | 0 | 0 | 529186 | 0 | 10104 | 10212 | 0 | 10212 | 20001 | 10100 |
10204 | 20030 | 20101 | 20101 | 0 | 0 | 10104 | 0 | 0 | 529186 | 0 | 10104 | 10212 | 0 | 10212 | 20001 | 10100 |
10204 | 20030 | 20101 | 20101 | 0 | 0 | 10104 | 0 | 0 | 529186 | 0 | 10104 | 10212 | 0 | 10212 | 20001 | 10100 |
10204 | 20030 | 20101 | 20101 | 0 | 0 | 10104 | 0 | 0 | 529186 | 0 | 10104 | 10212 | 0 | 10212 | 20001 | 10100 |
Result (median cycles for code): 2.0030
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
10024 | 20030 | 20021 | 20021 | 10025 | 529221 | 10025 | 10034 | 10020 | 20011 | 10010 |
10024 | 20030 | 20021 | 20021 | 10020 | 529253 | 10020 | 10020 | 10020 | 20011 | 10010 |
10024 | 20030 | 20021 | 20021 | 10020 | 529253 | 10020 | 10020 | 10020 | 20011 | 10010 |
10024 | 20030 | 20021 | 20021 | 10020 | 529253 | 10020 | 10020 | 10020 | 20011 | 10010 |
10024 | 20030 | 20021 | 20021 | 10020 | 529253 | 10020 | 10020 | 10020 | 20011 | 10010 |
10024 | 20030 | 20021 | 20021 | 10020 | 529253 | 10020 | 10020 | 10020 | 20011 | 10010 |
10024 | 20030 | 20021 | 20021 | 10020 | 529253 | 10020 | 10020 | 10020 | 20011 | 10010 |
10024 | 20030 | 20021 | 20021 | 10020 | 529253 | 10020 | 10020 | 10020 | 20011 | 10010 |
10024 | 20030 | 20021 | 20021 | 10020 | 529253 | 10020 | 10020 | 10020 | 20011 | 10010 |
10024 | 20030 | 20021 | 20021 | 10020 | 529253 | 10020 | 10020 | 10020 | 20011 | 10010 |
Count: 8
Code:
mvn w0, w8, ror #17 mvn w1, w8, ror #17 mvn w2, w8, ror #17 mvn w3, w8, ror #17 mvn w4, w8, ror #17 mvn w5, w8, ror #17 mvn w6, w8, ror #17 mvn w7, w8, ror #17
mov x8, 9
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.6675
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
80204 | 53429 | 160118 | 160118 | 80131 | 1360301 | 80130 | 80236 | 80236 | 160017 | 80100 |
80204 | 53404 | 160117 | 160117 | 80130 | 1360566 | 80130 | 80236 | 80236 | 160017 | 80100 |
80204 | 53404 | 160117 | 160117 | 80130 | 1360838 | 80130 | 80236 | 80236 | 160017 | 80100 |
80204 | 53404 | 160117 | 160117 | 80130 | 1360838 | 80130 | 80236 | 80236 | 160017 | 80100 |
80204 | 53404 | 160117 | 160117 | 80130 | 1360838 | 80130 | 80236 | 80236 | 160017 | 80100 |
80204 | 53404 | 160117 | 160117 | 80130 | 1360838 | 80130 | 80236 | 80236 | 160017 | 80100 |
80205 | 53433 | 160159 | 160159 | 80175 | 1361147 | 80176 | 80289 | 80236 | 160017 | 80100 |
80204 | 53404 | 160117 | 160117 | 80130 | 1360838 | 80130 | 80236 | 80236 | 160017 | 80100 |
62193 | 41450 | 124207 | 124207 | 62187 | 1360838 | 80130 | 80236 | 80236 | 160017 | 80100 |
80204 | 53404 | 160117 | 160117 | 80130 | 1360838 | 80130 | 80236 | 80236 | 160017 | 80100 |
Result (median cycles for code divided by count): 0.6671
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
80024 | 53378 | 160039 | 160039 | 80051 | 1359975 | 80051 | 80056 | 80020 | 160011 | 80010 |
80024 | 53371 | 160021 | 160021 | 80020 | 1359903 | 80020 | 80020 | 80020 | 160011 | 80010 |
80024 | 53371 | 160021 | 160021 | 80020 | 1359903 | 80020 | 80020 | 80020 | 160011 | 80010 |
80024 | 53371 | 160021 | 160021 | 80020 | 1359903 | 80020 | 80020 | 80020 | 160011 | 80010 |
80024 | 53371 | 160021 | 160021 | 80020 | 1359903 | 80020 | 80020 | 80230 | 160271 | 80010 |
80024 | 53371 | 160021 | 160021 | 80020 | 1359903 | 80020 | 80020 | 80020 | 160011 | 80010 |
80024 | 53371 | 160021 | 160021 | 80020 | 1359903 | 80020 | 80020 | 80020 | 160011 | 80010 |
80024 | 53371 | 160021 | 160021 | 80020 | 1359903 | 80020 | 80020 | 80020 | 160011 | 80010 |
80024 | 53371 | 160021 | 160021 | 80020 | 1359903 | 80020 | 80020 | 80020 | 160011 | 80010 |
80024 | 53371 | 160021 | 160021 | 80020 | 1361067 | 80225 | 80225 | 80020 | 160011 | 80010 |