Icestorm: LDRSH (register, sxtw, 64-bit) measurements

Code:

  ldrsh x0, [x6, w7, sxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	665	1025	1	1024	1000	8238	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	2000	1	1000
1004	554	1001	1	1000	1000	8238	1000	1000	2000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh x0, [x6, w7, sxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70155	40108	30107	10001	30130	10003	1859518	693887	40106	30210	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859398	693871	40106	30210	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40205	70084	40110	30108	10002	30135	10003	1859608	694079	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70162	40018	30017	10001	30040	10003	1859563	694699	40016	30032	10004	60044	20008	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70046	40012	30012	10000	30010	10052	1866071	697191	40194	30172	10052	60020	20000	30002	10000	30010
40024	70131	40024	30021	10003	30043	10119	1872177	702647	40428	30378	10121	60020	20000	30002	10000	30010
40024	70230	40036	30030	10006	30076	10053	1869365	701593	40195	30170	10053	60020	20000	30001	10000	30010
40024	70050	40012	30012	10000	30010	10000	1859841	694796	40010	30020	10000	60020	20000	30002	10000	30010

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh x0, [x6, w7, sxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70168	40108	30107	10001	30130	10003	1859593	693918	40106	30210	10004	60220	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10015	1859980	694139	40150	30247	10017	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40205	70086	40112	30110	10002	30135	10003	1860229	694325	40106	30212	10004	60224	20008	30003	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70253	40018	30017	10001	30040	10015	1860022	694720	40060	30069	10017	60040	20008	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70045	40012	30012	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40025	70072	40020	30018	10002	30045	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010

Test 4: throughput

Count: 8

Code:

  ldrsh x0, [x6, w7, sxtw]
  ldrsh x0, [x6, w7, sxtw]
  ldrsh x0, [x6, w7, sxtw]
  ldrsh x0, [x6, w7, sxtw]
  ldrsh x0, [x6, w7, sxtw]
  ldrsh x0, [x6, w7, sxtw]
  ldrsh x0, [x6, w7, sxtw]
  ldrsh x0, [x6, w7, sxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40162	80135	101	80034	100	80008	300	248136	80108	200	80012	200	160028	1	80000	100
80204	40050	80101	101	80000	100	80008	300	640142	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	160138	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640448	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640250	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	160024	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40279	80041	11	80030	10	80008	30	279868	80018	20	80012	20	160000	1	80000	10
80024	40051	80011	11	80000	10	80000	30	640112	80010	20	80000	20	160000	1	80000	10
80025	40103	80048	11	80037	10	80000	30	640112	80010	20	80000	20	160000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	160000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	160000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	160000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	160000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	160000	1	80000	10
80024	40056	80011	11	80000	10	80000	30	640778	80010	20	80000	20	160000	1	80000	10
80024	40055	80011	11	80000	10	80000	30	640328	80010	20	80000	20	160000	1	80000	10

LDRSH (register, sxtw, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations