Icestorm: CMN (register, 64-bit) measurements

Code:

  cmn x0, x1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	511	1001	1001	1000	3000	1000	1000	2000	1001
1004	405	1001	1001	1000	3000	1000	1000	2000	1001
1004	390	1001	1001	1000	3000	1000	1000	2000	1001
1004	391	1001	1001	1000	3000	1000	1000	2000	1001
1004	392	1001	1001	1000	3000	1000	1000	2000	1001
1004	391	1001	1001	1000	3000	1000	1000	2000	1001
1004	392	1001	1001	1000	3000	1000	1000	2000	1001
1004	395	1001	1001	1000	3000	1000	1000	2000	1001
1004	391	1001	1001	1000	3000	1000	1000	2000	1001
1004	391	1001	1001	1000	3000	1000	1000	2000	1001

Test 2: Latency 3->1

Chain cycles: 1

Code:

  cmn x0, x1
  cset x0, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20108	519338	20108	20214	30221	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519516	20018	20034	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519916	20050	20065	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010

Test 3: Latency 3->2

Chain cycles: 1

Code:

  cmn x0, x1
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20107	519311	20107	20214	30221	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30501	20085	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519476	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20018	519476	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010

Test 4: throughput

Count: 8

Code:

  cmn x0, x1
  cmn x0, x1
  cmn x0, x1
  cmn x0, x1
  cmn x0, x1
  cmn x0, x1
  cmn x0, x1
  cmn x0, x1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3635

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	29211	80112	80112	80117	240351	80117	80218	160234	80012	100
80204	29155	80113	80113	80117	240354	80118	80220	160240	80015	100
80204	29035	80115	80115	80119	240357	80119	80220	160240	80015	100
80205	29096	80150	80150	80155	240354	80118	80220	160240	80013	100
80204	29147	80115	80115	80120	240357	80119	80220	160240	80013	100
80204	29054	80112	80112	80117	240354	80118	80220	160240	80015	100
80204	29154	80113	80113	80118	240354	80118	80220	160240	80015	100
80204	29060	80115	80115	80120	240360	80120	80220	160240	80013	100
80204	29166	80115	80115	80120	240354	80118	80220	160240	80013	100
80204	29072	80112	80112	80117	240354	80118	80220	160240	80013	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3631

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	30145	80035	80035	0	80040	240079	80020	80020	160020	80011	10
80024	29073	80021	80021	0	80020	240080	80020	80020	160020	80011	10
80024	28997	80021	80021	0	80020	240114	80020	80020	160020	80011	10
80024	29117	80021	80021	0	80020	240104	80020	80020	160020	80011	10
80024	28980	80021	80021	0	80020	240107	80020	80020	160020	80011	10
80024	29087	80021	80021	0	80020	240090	80020	80020	160020	80011	10
80024	28973	80021	80021	0	80020	240109	80020	80020	160020	80011	10
80024	29109	80021	80021	0	80020	240123	80020	80020	160020	80011	10
80024	28982	80021	80021	0	80020	240106	80020	80020	160020	80011	10
80024	29099	80021	80021	0	80020	240106	80020	80020	160020	80011	10

CMN (register, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations