Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDR (64-bit)

Test 1: uops

Code:

  ldr x0, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	688	1021	1	1020	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	1000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldr x0, [x6]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40206	70252	40116	30113	10003	30162	10003	1860202	694293	40106	30212	10004	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10015	1859980	694147	40150	30247	10017	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10015	1859980	694196	40150	30247	10017	60224	10004	30003	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70265	40018	30017	10001	30040	10003	1859488	694643	40016	30032	10004	60044	10004	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	10000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	10000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	10000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60122	10017	30008	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	10000	30002	10000	30010
40024	70046	40012	30012	10000	30010	10000	1859787	694774	40010	30020	10000	60020	10000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	10000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	10000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	10000	30002	10000	30010

Test 3: throughput

Count: 8

Code:

  ldr x0, [x6]
  ldr x0, [x6]
  ldr x0, [x6]
  ldr x0, [x6]
  ldr x0, [x6]
  ldr x0, [x6]
  ldr x0, [x6]
  ldr x0, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40519	80131	101	80030	100	80008	300	326561	80108	200	80012	200	80012	1	80000	100
80204	40055	80105	101	80004	100	80008	300	640142	80108	200	80012	200	80012	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	80012	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	80012	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	80012	1	80000	100
80204	40049	80101	101	80000	100	80008	300	640142	80108	200	80012	200	80012	1	80000	100
80204	40052	80101	101	80000	100	80008	300	336190	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	80012	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40473	80041	11	80030	10	80008	30	436819	80018	20	80012	20	80228	1	80000	10
80024	40060	80011	11	80000	10	80000	30	640040	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640364	80010	20	80000	20	80012	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	80010	20	80000	20	80000	1	80000	10
80024	40075	80011	11	80000	10	80000	30	640238	80010	20	80000	20	80000	1	80000	10