Icestorm: EOR (register, lsr, 32-bit) measurements

Code:

  eor w0, w0, w1, lsr #17

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2078	2022	2022	1035	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2078	2022	2022	1035	52265	1000	1000	2000	2001	1000
1004	2078	2022	2022	1035	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000

Test 2: Latency 1->2

Code:

  eor w0, w0, w1, lsr #17

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	20030	20101	20101	10104	529093	10104	10210	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100
10204	20224	20187	20187	10246	529186	10104	10212	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	20030	20021	20021	10025	529197	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010

Test 3: Latency 1->3

Code:

  eor w0, w1, w0, lsr #17

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	20030	20101	20101	10104	529071	10105	10214	20302	20016	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100
10204	20030	20101	20101	10104	529186	10104	10212	20224	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	20030	20021	20021	10025	529220	10025	10034	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10025	20060	20035	20035	10059	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529253	10020	10020	20020	20011	10010

Test 4: throughput

Count: 8

Code:

  eor w0, w8, w9, lsr #17
  eor w1, w8, w9, lsr #17
  eor w2, w8, w9, lsr #17
  eor w3, w8, w9, lsr #17
  eor w4, w8, w9, lsr #17
  eor w5, w8, w9, lsr #17
  eor w6, w8, w9, lsr #17
  eor w7, w8, w9, lsr #17

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	53429	160118	160118	80131	0	1360563	0	80129	80234	0	160272	160017	80100
80204	53404	160117	160117	80130	0	1360838	0	80130	80236	0	160272	160017	80100
80204	53404	160117	160117	80130	0	1360838	0	80130	80236	0	160272	160017	80100
80204	53404	160117	160117	80130	0	1360838	0	80130	80236	0	160376	160065	80100
80204	53404	160117	160117	80130	0	1360593	0	80131	80238	0	160268	160015	80100
80204	53415	160116	160116	80129	0	1360838	0	80130	80236	0	160272	160017	80100
80204	53404	160117	160117	80130	0	1360838	0	80130	80236	0	160272	160017	80100
80204	53404	160117	160117	80130	0	1360838	0	80130	80236	0	160272	160017	80100
80204	53404	160117	160117	80130	0	1360838	0	80130	80236	0	160272	160017	80100
80204	53404	160117	160117	80130	0	1360838	0	80130	80236	0	160272	160017	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6671

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	53378	160039	160039	80051	1359646	80020	80020	160020	160011	80010
80024	53371	160021	160021	80020	1359903	80020	80020	160020	160011	80010
80024	53371	160021	160021	80020	1359903	80020	80020	160020	160011	80010
80024	53371	160021	160021	80020	1359903	80020	80020	160020	160011	80010
80024	53371	160021	160021	80020	1359903	80020	80020	160020	160011	80010
80024	53580	160282	160282	80228	1359903	80020	80020	160020	160011	80010
80024	53371	160021	160021	80020	1359903	80020	80020	160020	160011	80010
80025	53409	160084	160084	80098	1359903	80020	80020	160020	160011	80010
80024	53371	160021	160021	80020	1359903	80020	80020	160020	160011	80010
80024	53371	160021	160021	80020	1359903	80020	80020	160020	160011	80010

EOR (register, lsr, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations