Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMP (uxtb, 32-bit)

Test 1: uops

Code:

  cmp w0, w1, uxtb
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)
1004698200120011000146781000100020002001
1004698200120011000146781000100020002001
1004698200120011000146781000100020002001
1004698200120011000146781000100020002001
1004698200120011000146781000100020002001
1004698200120011000146781000100020002001
1004698200120011000146781000100020002001
1004698200120011000146781000100020002001
1004698200120011000146781000100020002001
1004698200120011000146781000100020002001

Test 2: Latency 3->1

Chain cycles: 1

Code:

  cmp w0, w1, uxtb
  cset x0, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20204300303010130101201057892912010520210302153000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20024300303001130011200157893812001520030300203000110010
20024300303001130011200107894382001020020300203000110010
20024300303001130011200107894382001020020300203000110010
20024300303001130011200107894382001020020300203000110010
20024300303001130011200107894382001020020300203000110010
20024300303001130011200107894382001020020300203000110010
20024300303001130011200107894382001020020300203000110010
20024300303001130011200107894382001020020300203000110010
20024300303001130011200107894382001020020300203000110010
20024300303001130011200107894382001020020300203000110010

Test 3: Latency 3->2

Chain cycles: 1

Code:

  cmp w0, w1, uxtb
  cset x1, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20204300303010130101201067892312010520210302153000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20024300303001130011200157893812001520030300383000110010
20024300303001130011200157894592001520032300383000110010
20024300303001130011200157894592001520032300383000110010
20024300303001130011200157894592001520032300383000110010
20024300303001130011200157898042005120076300383000110010
20024300303001130011200157894592001520032300383000110010
20024300303001130011200157894592001520032300383000110010
20024300303001130011200157894592001520032300383000110010
20024300303001130011200157894592001520032300383000110010
20024300303001130011200157894592001520032300383000110010

Test 4: throughput

Count: 8

Code:

  cmp w0, w1, uxtb
  cmp w0, w1, uxtb
  cmp w0, w1, uxtb
  cmp w0, w1, uxtb
  cmp w0, w1, uxtb
  cmp w0, w1, uxtb
  cmp w0, w1, uxtb
  cmp w0, w1, uxtb
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
80204534271601181601188012611775998012580226160328160059100
80204534021601141601148012311776778012580226160248160014100
80204534021601141601148012311776238012380224160248160014100
80204534021601141601148012311776518012380224160248160014100
80204534021601141601148012311776198012380224160248160014100
80204534021601141601148012311776478012380224160248160014100
80204534021601141601148012311776198012380224160248160014100
80205534361601651601658016811776558012380224160248160014100
80204534021601141601148012311776238012380224160248160014100
80204534021601141601148012311776518012380224160248160014100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6671

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
8002553409160079160079800801172240800468004616002001600110010
8002453371160021160021800201170032800208002016002001600110010
8002453410160044160044800531170032800208002016002001600110010
8002453371160021160021800201170032800208002016002001600110010
8002453371160021160021800201170032800208002016002001600110010
8002453371160021160021800201170032800208002016002001600110010
8002453371160021160021800201170032800208002016002001600110010
8002453371160021160021800201170032800208002016002001600110010
8002453371160021160021800201170032800208002016002001600110010
8002453371160021160021800201170032800208002016002001600110010