Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

PRFM (register, PLDL2STRM)

Test 1: uops

Code:

  prfm pldl2strm, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1004	2037	1001	1	1000	1000	34082	1000	1000	1000	1	1000
1004	2058	1001	1	1000	1000	34136	1000	1000	1000	1	1000
1004	2058	1001	1	1000	1000	34136	1000	1000	1000	1	1000
1004	2058	1001	1	1000	1000	34136	1000	1000	1000	1	1000
1004	2058	1001	1	1000	1000	34136	1000	1000	1000	1	1000
1004	2058	1001	1	1000	1000	34136	1000	1000	1000	1	1000
1004	2058	1001	1	1000	1000	34136	1000	1000	1000	1	1000
1004	2058	1001	1	1000	1000	34136	1000	1000	1000	1	1000
1004	2058	1001	1	1000	1000	34136	1000	1000	1000	1	1000
1004	2058	1001	1	1000	1000	34136	1000	1000	1000	1	1000

Test 2: throughput

Code:

  prfm pldl2strm, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.9983

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20204	20314	20105	10105	10000	10106	10000	61224	351269	20101	10203	10003	10209	10009	10007	10000	10100
20204	20118	20103	10103	10000	10108	10000	61165	347595	20106	10208	10008	10213	10013	10006	10000	10100
20204	19992	20104	10104	10000	10107	10004	61911	345629	20113	10211	10011	10206	10006	10002	10000	10100
20204	19865	20101	10101	10000	10102	10000	61293	348863	20100	10202	10002	10207	10007	10003	10000	10100
20204	20043	20102	10102	10000	10106	10006	61299	351729	20118	10214	10014	10202	10002	10001	10000	10100
20204	20119	20105	10105	10000	10110	10000	61256	350429	20103	10205	10005	10203	10004	10001	10000	10100
20204	19971	20101	10101	10000	10102	10000	61544	346833	20106	10208	10008	10202	10002	10001	10000	10100
20204	20030	20101	10101	10000	10100	10002	61514	347503	20110	10210	10010	10210	10010	10003	10000	10100
20204	19948	20102	10102	10000	10106	10002	61942	345095	20110	10210	10010	10214	10014	10006	10000	10100
20204	19983	20106	10106	10000	10112	10006	61535	348125	20118	10214	10014	10214	10014	10006	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0023

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20024	20924	20011	10011	10000	10013	10004	60440	345879	20023	10031	10012	10020	10000	10001	10000	10010
20024	20023	20011	10011	10000	10010	10000	61108	348705	20010	10020	10000	10020	10000	10001	10000	10010
20024	20023	20011	10011	10000	10010	10000	61108	348705	20010	10020	10000	10020	10000	10001	10000	10010
20024	20023	20011	10011	10000	10010	10000	61108	348705	20010	10020	10000	10020	10000	10001	10000	10010
20024	20023	20011	10011	10000	10010	10000	61108	348705	20010	10020	10000	10020	10000	10001	10000	10010
20024	20023	20011	10011	10000	10010	10000	61108	348705	20010	10020	10000	10020	10000	10001	10000	10010
20024	20023	20011	10011	10000	10010	10000	61108	348705	20010	10020	10000	10020	10000	10001	10000	10010
20024	20023	20011	10011	10000	10010	10000	61108	348705	20010	10020	10000	10020	10000	10001	10000	10010
20024	19860	20011	10011	10000	10010	10000	61491	346271	20010	10020	10000	10020	10000	10001	10000	10010
20024	19976	20011	10011	10000	10010	10000	60894	349281	20010	10020	10000	10020	10000	10001	10000	10010

Test 3: throughput

Code:

  prfm pldl2strm, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0503

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10204	20467	10101	101	10000	100	10002	300	357166	10102	200	10012	200	10012	1	10000	100
10204	20408	10101	101	10000	100	10000	300	357346	10100	200	10004	200	10004	1	10000	100
10204	20482	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10012	1	10000	100
10204	20503	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10012	1	10000	100
10204	20503	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10012	1	10000	100
10204	20503	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10012	1	10000	100
10204	20503	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10012	1	10000	100
10204	20503	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10012	1	10000	100
10204	20503	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10012	1	10000	100
10204	20503	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.8718

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10024	19535	10011	11	10000	10	10006	30	325270	10016	20	10012	20	10014	1	10000	10
10024	18718	10011	11	10000	10	10000	30	325246	10010	20	10000	20	10000	1	10000	10
10024	18718	10011	11	10000	10	10000	30	325246	10010	20	10000	20	10000	1	10000	10
10024	18718	10011	11	10000	10	10000	30	325246	10010	20	10000	20	10000	1	10000	10
10024	18718	10011	11	10000	10	10000	30	325246	10010	20	10000	20	10000	1	10000	10
10024	18718	10011	11	10000	10	10000	30	325246	10010	20	10000	20	10000	1	10000	10
10024	18718	10011	11	10000	10	10000	30	325246	10010	20	10000	20	10000	1	10000	10
10024	18718	10011	11	10000	10	10000	30	325246	10010	20	10000	20	10000	1	10000	10
10024	18718	10011	11	10000	10	10000	30	325246	10010	20	10000	20	10000	1	10000	10
10024	18718	10011	11	10000	10	10000	30	325246	10010	20	10000	20	10000	1	10000	10