Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CSEL (64-bit)

Test 1: uops

Code:

  csel x0, x0, x1, hi
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
100410301001100110002560310001000300010011000
100410301001100110002560310001000300010011000
100410301001100110002560310001000300010011000
100410301001100110002560310001000300010011000
100410301001100110002560310001000300010011000
100410301001100110002560310001000300010011000
100410301001100110002560310001000300010011000
100410301001100110002560310001000300010011000
100410301001100110002560310001000300010011000
100410301001100110002560310001000300010011000

Test 2: Latency 1->2

Code:

  csel x0, x0, x1, hi
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204100301010110101101072593291010710214302421000110100
10204100301010110101101072595391010710212302361000110100
10204100301010110101101072595391010710212302361000110100
10204100301010110101101072595391010710212302361000110100
10204100301010110101101072595391010710212302361000110100
10204100301010110101101072595391010710212302361000110100
10204100301010110101101072595391010710212302361000110100
10204100301010110101101072595391010710212302361000110100
10204100301010110101101072595391010710212302361000110100
10204100301010110101101072595391010710212302361000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024100301002110021100282595281003010038300201001110010
10024100301002110021100202595911002010020300201001110010
10024100301002110021100202595911002010020300201001110010
10024100301002110021100202595911002010020300201001110010
10024100301002110021100202595911002010020300201001110010
10024100301002110021100202595911002010020300201001110010
10024100301002110021100202595911002010020300201001110010
10024100301002110021100202595911002010020300201001110010
10024100301002110021100202599461006810080302001002510010
10024100301002110021100202595911002010020300201001110010

Test 3: Latency 1->3

Code:

  csel x0, x1, x0, hi
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204100301010110101101082594151010710214302361000110100
10204100301010110101101072595391010710212305151004310100
10204100301010110101101072595391010710212302361000110100
10204100301010110101101072595391010710212302361000110100
10204100301010110101101072595391010710212302361000110100
10204100301010110101101072595391010710212302361000110100
10204100301010110101101072595391010710212302361000110100
10204100301010110101101072595391010710212302361000110100
10204100301010110101101072595391010710212302361000110100
10204100301010110101101072595391010710212302361000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024100301002110021100282594901002810034300201001110010
10024100301002110021100202595911002010020300201001110010
10024100301002110021100202595911002010020300201001110010
10024100301002110021100202595911002010020300201001110010
10024100301002110021100202595911002010020300201001110010
10024100301002110021100202595911002010020300201001110010
10024100301002110021100202595911002010020300201001110010
10024100301002110021100202595911002010020300201001110010
10024100301002110021100202595911002010020300201001110010
10024100301002110021100202595911002010020300201001110010

Test 4: Latency 1->4

Chain cycles: 1

Code:

  csel x0, x1, x2, hi
  tst x0, 1
  mov x0, 1
  mov x1, 2
  mov x2, 3

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20204200302020120201202085191902020820216402322010110100
20204200302020120201202085194482020820216402322010110100
20204200302020120201202085194482020820216402322010110100
20204200302020120201202085194482020820216402322010110100
20204200302020120201202085194482020820216402322010110100
20204200302020120201202085197662024820260402322010110100
20204200302020120201202085197762025020262402322010110100
20204200302020120201202095194482020820216402322010110100
20204200302020120201202085194482020820216402322010110100
20204200302020120201202085194482020820216402322010110100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20024200302002120021200285195002002920036400202001110010
20024200302002120021200205195912002020020400202001110010
20024200302002120021200205195912002020020400202001110010
20024200302002120021200205195912002020020400202001110010
20024200302002120021200205195912002020020400202001110010
20024200302002120021200205195912002020020400202001110010
20024200302002120021200205195912002020020400202001110010
20024200302002120021200205195912002020020400202001110010
20024200302002120021200205195912002020020400202001110010
20024200302002120021200205195912002020020400202001110010

Test 5: throughput

Count: 8

Code:

  csel x0, x8, x9, hi
  csel x1, x8, x9, hi
  csel x2, x8, x9, hi
  csel x3, x8, x9, hi
  csel x4, x8, x9, hi
  csel x5, x8, x9, hi
  csel x6, x8, x9, hi
  csel x7, x8, x9, hi
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
802042687380115801158012029110080120802222402638001480100
802042674280114801148011929323680120802242402728001580100
802042673780115801158012029323680120802212402728001580100
802042673780115801158012029323680120802242402728001580100
802042673780115801158012029323680120802242402728001580100
802042673780115801158012029323680120802242402728001580100
802042673780115801158012029323680120802242402728001580100
802042673780115801158012029323680120802242402728001580100
802042673780115801158012029323680120802242402728001580100
802042673780115801158012029323680120802242402728001580100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
800242800480038800388005230941680020800202400208001180010
800242677280021800218002042678080020800202400208001180010
800242671980021800218002042678080020800202400208001180010
800242671980021800218002042678080020800202400208001180010
800242675080021800218002042678080020800202400208001180010
800242671980021800218002042678080020800202400208001180010
800242671980021800218002042678080020800202400208001180010
800242671980021800218002042678080020800202400208001180010
800242671980021800218002042678080020800202400208001180010
800242671980021800218002042678080020800202400208001180010