Icestorm: SDIV (medium, 64-bit) measurements

Code:

  sdiv x0, x1, x2

Initialization

  mov x1, #0xffffffff
  mov x2, #3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	13030	2001	2001	1000	115532	1000	1000	2000	2001	1000
1004	13030	2001	2001	1000	115532	1000	1000	2000	2001	1000
1004	13030	2001	2001	1000	115532	1000	1000	2000	2001	1000
1004	13030	2001	2001	1000	115532	1000	1000	2000	2001	1000
1004	13030	2001	2001	1000	115532	1000	1000	2000	2001	1000
1004	13030	2001	2001	1000	115532	1000	1000	2000	2001	1000
1004	13030	2001	2001	1000	115532	1000	1000	2000	2001	1000
1004	13030	2001	2001	1000	115532	1000	1000	2000	2001	1000
1004	13030	2001	2001	1000	115532	1000	1000	2000	2001	1000
1004	13030	2001	2001	1000	115532	1000	1000	2000	2001	1000

Test 2: Latency 1->2

Chain cycles: 2

Code:

  sdiv x0, x1, x2
  eor x1, x1, x0
  eor x1, x1, x0

Initialization

  mov x1, #0xffffffff
  mov x2, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 13.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30204	150030	40201	40201	30203	0	4018014	0	30203	30210	0	60220	40101	30100
30204	150030	40201	40201	30203	0	4018070	0	30203	30212	0	60224	40101	30100
30205	150060	40204	40204	30231	0	4018070	0	30203	30212	0	60304	40104	30100
30204	150030	40201	40201	30203	0	4018070	0	30203	30212	0	60224	40101	30100
30204	150030	40201	40201	30203	0	4018070	0	30203	30212	0	60224	40101	30100
30204	150030	40201	40201	30203	0	4018070	0	30203	30212	0	60224	40101	30100
30205	150060	40204	40204	30230	0	4018070	0	30203	30212	0	60224	40101	30100
30204	150030	40201	40201	30203	0	4018070	0	30203	30212	0	60224	40101	30100
30204	150030	40201	40201	30203	0	4018070	0	30203	30212	0	60224	40101	30100
30204	150030	40201	40201	30203	0	4018070	0	30203	30212	0	60224	40101	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 13.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30024	150030	40011	40011	30013	0	4018298	0	0	30010	30020	0	0	60020	40001	30010
30024	150030	40011	40011	30010	0	4018329	0	0	30010	30020	0	0	60020	40001	30010
30024	150030	40011	40011	30010	0	4018329	0	0	30010	30020	0	0	60116	40004	30010
30024	150030	40011	40011	30010	0	4018329	0	0	30010	30020	0	0	60020	40001	30010
30024	150030	40011	40011	30010	0	4018329	0	0	30010	30020	0	0	60020	40001	30010
30024	150030	40011	40011	30010	0	4018329	0	0	30010	30020	0	0	60020	40001	30010
30024	150030	40011	40011	30010	0	4018329	0	0	30010	30020	0	0	60188	40007	30010
30024	150030	40011	40011	30010	0	4018329	0	0	30010	30020	0	0	60046	40001	30010
30024	150030	40011	40011	30010	0	4018329	0	0	30010	30020	0	0	60020	40001	30010
30024	150030	40011	40011	30010	0	4018329	0	0	30010	30020	0	0	60020	40001	30010

Test 3: Latency 1->3

Chain cycles: 2

Code:

  sdiv x0, x1, x2
  eor x2, x2, x0
  eor x2, x2, x0

Initialization

  mov x1, #0xffffffff
  mov x2, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 13.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
30204	150030	40201	40201	30203	4018014	30203	30210	60224	0	0	40101	0	0	30100
30204	150030	40201	40201	30203	4018070	30203	30212	60224	0	0	40101	0	0	30100
30204	150030	40201	40201	30203	4018428	30230	30247	60224	0	0	40101	0	0	30100
30204	150030	40201	40201	30203	4018070	30203	30212	60224	0	0	40101	0	0	30100
30204	150030	40201	40201	30203	4018070	30203	30212	60224	0	0	40101	0	0	30100
30204	150030	40201	40201	30203	4018070	30203	30212	60224	0	0	40101	0	0	30100
30204	150030	40201	40201	30203	4018405	30232	30248	60224	0	0	40101	0	0	30100
30204	150030	40201	40201	30203	4018402	30231	30248	60224	0	0	40101	0	0	30100
30204	150030	40201	40201	30203	4018070	30203	30212	60224	0	0	40101	0	0	30100
30204	150030	40201	40201	30203	4018070	30203	30212	60224	0	0	40101	0	0	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 13.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30024	150030	40011	40011	30013	4018298	30010	30020	60020	40001	30010
30024	150030	40011	40011	30010	4018329	30010	30020	60020	40001	30010
30024	150030	40011	40011	30010	4018329	30010	30020	60020	40001	30010
30024	150030	40011	40011	30010	4018329	30010	30020	60116	40004	30010
30024	150030	40011	40011	30010	4018329	30010	30020	60020	40001	30010
30024	150030	40011	40011	30010	4018329	30010	30020	60020	40001	30010
30024	150030	40011	40011	30010	4018329	30010	30020	60020	40001	30010
30024	150030	40011	40011	30010	4019019	30069	30106	60116	40004	30010
30024	150030	40011	40011	30010	4018329	30010	30020	60020	40001	30010
30024	150030	40011	40011	30010	4018329	30010	30020	60020	40001	30010

Test 4: throughput

Code:

  sdiv x0, x1, x2

Initialization

  mov x1, #0xffffffff
  mov x2, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10204	130030	20101	20101	0	0	10100	0	1159948	10109	10226	20212	0	20001	0	0	10100
10205	130060	20104	20104	0	0	10109	0	1159832	10100	10208	20216	0	20001	0	0	10100
10204	130030	20101	20101	0	0	10100	0	1159832	10100	10208	20216	0	20001	0	0	10100
10204	130030	20101	20101	0	0	10100	0	1159832	10100	10208	20216	0	20001	0	0	10100
10204	130030	20101	20101	0	0	10100	0	1159832	10100	10208	20216	0	20001	0	0	10100
10204	130030	20101	20101	0	0	10100	0	1159832	10100	10208	20216	0	20001	0	0	10100
10204	130030	20101	20101	0	0	10100	0	1159832	10100	10208	20216	0	20001	0	0	10100
10204	130030	20101	20101	0	0	10100	0	1159832	10100	10208	20216	0	20001	0	0	10100
10204	130030	20101	20101	0	0	10100	0	1159832	10100	10208	20216	0	20001	0	0	10100
10204	130030	20101	20101	0	0	10100	0	1159832	10100	10208	20216	0	20001	0	0	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	130030	20021	20021	0	10020	1159592	10020	10028	20020	20011	10010
10024	130030	20021	20021	0	10020	1159592	10020	10020	20020	20011	10010
10025	130060	20024	20024	0	10029	1159592	10020	10020	20020	20011	10010
10024	130030	20021	20021	0	10020	1159592	10020	10020	20020	20011	10010
10024	130030	20021	20021	0	10020	1159592	10020	10020	20020	20011	10010
10024	130030	20021	20021	0	10020	1159592	10020	10020	20020	20011	10010
10024	130030	20021	20021	0	10020	1159592	10020	10020	20020	20011	10010
10024	130030	20021	20021	0	10020	1159592	10020	10020	20020	20011	10010
10024	130030	20021	20021	0	10020	1159592	10020	10020	20020	20011	10010
10024	130030	20021	20021	0	10020	1159708	10029	10044	20020	20011	10010

SDIV (medium, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations