Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

STNP (32-bit)

Test 1: uops

Code:

  stnp w0, w1, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1547	1019	1	1018	1000	17279	1000	1000	3000	1	1000
1004	1061	1001	1	1000	1000	17279	1000	1000	3000	1	1000
1004	1061	1001	1	1000	1000	17279	1000	1000	3000	1	1000
1004	1061	1001	1	1000	1000	17279	1000	1000	3000	1	1000
1004	1061	1001	1	1000	1000	17279	1000	1000	3000	1	1000
1004	1061	1001	1	1000	1000	17279	1000	1000	3000	1	1000
1004	1061	1001	1	1000	1000	17279	1000	1000	3000	1	1000
1004	1061	1001	1	1000	1000	17279	1000	1000	3000	1	1000
1004	1061	1001	1	1000	1000	17279	1000	1000	3000	1	1000
1004	1061	1001	1	1000	1000	17279	1000	1000	3000	1	1000

Test 2: throughput

Code:

  stnp w0, w1, [x6]
  add x6, x6, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0038

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20209	11234	20404	10314	10090	10315	10003	120713	169980	20110	10209	10009	10207	30021	10001	10000	10100
20204	10038	20101	10101	10000	10108	10003	155395	169931	20111	10208	10008	10208	30024	10001	10000	10100
20204	10038	20101	10101	10000	10108	10003	155395	169931	20111	10208	10008	10208	30024	10001	10000	10100
20204	10038	20101	10101	10000	10108	10003	155395	169931	20111	10208	10008	10208	30024	10001	10000	10100
20204	10038	20101	10101	10000	10108	10003	155395	169931	20111	10208	10008	10208	30024	10001	10000	10100
20204	10038	20101	10101	10000	10108	10003	155395	169931	20111	10208	10008	10208	30024	10001	10000	10100
20204	10038	20101	10101	10000	10108	10003	155395	169931	20111	10208	10008	10208	30024	10001	10000	10100
20204	10038	20101	10101	10000	10108	10003	155395	169931	20111	10208	10008	10208	30024	10001	10000	10100
20204	10038	20101	10101	10000	10108	10003	155395	169931	20111	10208	10008	10208	30024	10001	10000	10100
20204	10038	20101	10101	10000	10108	10003	155395	169931	20111	10208	10008	10208	30024	10001	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20029	10880	20313	10223	10090	10224	10003	62294	170417	20020	10027	10008	10020	30000	10001	10000	10010
20024	10056	20011	10011	10000	10010	10000	102186	170083	20010	10020	10000	10020	30000	10001	10000	10010
20024	10042	20011	10011	10000	10010	10000	102186	170083	20010	10020	10000	10059	30117	10032	10000	10010
20024	10047	20011	10011	10000	10010	10000	92917	170083	20010	10020	10000	10020	30000	10001	10000	10010
20024	10042	20011	10011	10000	10010	10000	102186	170083	20010	10020	10000	10020	30000	10001	10000	10010
20024	10042	20011	10011	10000	10010	10000	102186	170083	20010	10020	10000	10020	30000	10001	10000	10010
20024	10042	20011	10011	10000	10010	10000	102186	170083	20010	10020	10000	10020	30000	10001	10000	10010
20024	10042	20011	10011	10000	10010	10000	102186	170083	20010	10020	10000	10020	30000	10001	10000	10010
20024	10042	20011	10011	10000	10010	10000	102186	170083	20010	10020	10000	10020	30000	10001	10000	10010
20024	10042	20011	10011	10000	10010	10000	102186	170083	20010	10020	10000	10020	30000	10001	10000	10010

Test 3: throughput

Code:

  stnp w0, w1, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0401

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10205	10149	10119	101	10018	100	10001	300	176544	10101	200	10008	202	30126	2	10000	100
10204	10408	10101	101	10000	100	10001	300	176366	10101	200	10008	200	30024	1	10000	100
10204	10401	10101	101	10000	100	10001	300	176544	10101	200	10008	200	30024	1	10000	100
10204	10401	10101	101	10000	100	10001	300	176402	10101	200	10008	200	30024	1	10000	100
10204	10408	10101	101	10000	100	10001	300	176544	10101	200	10008	200	30024	1	10000	100
10204	10401	10101	101	10000	100	10001	300	176402	10101	200	10008	200	30024	1	10000	100
10204	10401	10101	101	10000	100	10001	300	176402	10101	200	10008	200	30024	1	10000	100
10204	10401	10101	101	10000	100	10001	300	180146	10101	200	10008	200	30024	1	10000	100
10204	10401	10101	101	10000	100	10001	300	176402	10101	200	10008	200	30024	1	10000	100
10204	10401	10101	101	10000	100	10001	300	176402	10101	200	10008	200	30024	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0408

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10025	10146	10029	11	10018	10	10001	30	176508	10011	20	10008	20	30000	1	10000	10
10024	10408	10011	11	10000	10	10000	30	176541	10010	20	10000	20	30000	1	10000	10
10024	10408	10011	11	10000	10	10000	30	176541	10010	20	10000	20	30024	1	10000	10
10024	10408	10011	11	10000	10	10000	30	176541	10010	20	10000	20	30000	1	10000	10
10024	10408	10011	11	10000	10	10000	30	176541	10010	20	10000	20	30000	1	10000	10
10024	10408	10011	11	10000	10	10000	30	176541	10010	20	10000	20	30000	1	10000	10
10024	10408	10011	11	10000	10	10000	30	176541	10010	20	10000	20	30000	1	10000	10
10024	10408	10011	11	10000	10	10000	30	176541	10010	20	10000	20	30000	1	10000	10
10024	10408	10011	11	10000	10	10000	30	176541	10010	20	10000	20	30000	1	10000	10
10024	10408	10011	11	10000	10	10000	30	176541	10010	20	10000	20	30000	1	10000	10