Icestorm: SMULL measurements

Code:

  smull x0, w0, w1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000

Test 2: Latency 1->2

Code:

  smull x0, w0, w1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	30030	10101	10101	10100	260144	10100	10206	20212	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	30030	10021	10021	10020	259907	10020	10030	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	260532	10080	10110	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010
10024	30117	10035	10035	10050	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	260224	10050	10060	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010
10024	30074	10028	10028	10035	259916	10020	10020	20020	10011	10010
10024	30116	10035	10035	10050	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	260070	10035	10040	20020	10011	10010

Test 3: Latency 1->3

Code:

  smull x0, w1, w0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	30030	10101	10101	10100	260144	10100	10206	20258	10006	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	30030	10021	10021	10020	259907	10020	10030	20040	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20084	10016	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010

Test 4: throughput

Count: 8

Code:

  smull x0, w8, w9
  smull x1, w8, w9
  smull x2, w8, w9
  smull x3, w8, w9
  smull x4, w8, w9
  smull x5, w8, w9
  smull x6, w8, w9
  smull x7, w8, w9

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80205	80086	80120	80120	80124	240315	80105	80210	160224	80004	80100
80205	80076	80120	80120	80124	240315	80105	80212	160224	80004	80100
80204	80034	80104	80104	80105	240315	80105	80212	160224	80004	80100
80205	80066	80122	80122	80126	240315	80105	80212	160220	80004	80100
80205	80076	80120	80120	80124	240315	80105	80212	160224	80004	80100
80204	80034	80104	80104	80105	240315	80105	80212	160272	80020	80100
80204	80034	80104	80104	80105	240315	80105	80212	160224	80004	80100
80204	80034	80104	80104	80105	240315	80105	80212	160224	80004	80100
80204	80034	80104	80104	80105	240315	80105	80212	160224	80004	80100
80204	80034	80104	80104	80105	240369	80124	80236	160224	80004	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	80057	80025	80025	80026	0	240078	0	0	80026	80034	0	0	160020	80011	80010
80024	80032	80021	80021	80020	0	240060	0	0	80020	80020	0	0	160020	80011	80010
80024	80032	80021	80021	80020	0	240060	0	0	80020	80020	0	0	160020	80011	80010
80024	80032	80021	80021	80020	0	240060	0	0	80020	80020	0	0	160020	80011	80010
80024	80032	80021	80021	80020	0	240060	0	0	80020	80020	0	0	160100	80031	80010
80024	80032	80021	80021	80020	0	240060	0	0	80020	80020	0	0	160020	80011	80010
80024	80032	80021	80021	80020	0	240060	0	0	80020	80020	0	0	160020	80011	80010
80024	80032	80021	80021	80020	0	240060	0	0	80020	80020	0	0	160090	80031	80010
80024	80032	80021	80021	80020	0	240060	0	0	80020	80020	0	0	160020	80011	80010
80024	80032	80021	80021	80020	0	240060	0	0	80020	80020	0	0	160020	80011	80010

SMULL

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations